X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=Generate.hs;fp=Generate.hs;h=8065363ca53b8ec7965e1636f4f6ba16e6907532;hb=4d96e10ba2805470597642cf4c2ba797eda1b1f9;hp=75bea2462a5a91dc0976b7ab19e0631de6dc3381;hpb=6fffdcf32a54a6372442d22a87537ee9733073ad;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git diff --git a/Generate.hs b/Generate.hs index 75bea24..8065363 100644 --- a/Generate.hs +++ b/Generate.hs @@ -48,10 +48,10 @@ genMapCall entity [arg, res] = return $ genSm genScheme = AST.ForGn nPar range -- Get the entity name and port names entity_id = ent_id entity - argport = map (Monad.liftM fst) (ent_args entity) + argports = map (Monad.liftM fst) (ent_args entity) resport = (Monad.liftM fst) (ent_res entity) -- Assign the ports - inport = mkAssocElemIndexed (head argport) (varToString arg) nPar + inport = mkAssocElemIndexed (argports!!0) (varToString arg) nPar outport = mkAssocElemIndexed resport (varToString res) nPar clk_port = mkAssocElem (Just $ mkVHDLExtId "clk") "clk" portassigns = Maybe.catMaybes [inport,outport,clk_port] @@ -60,6 +60,34 @@ genMapCall entity [arg, res] = return $ genSm compins = mkComponentInst mapLabel entity_id portassigns -- Return the generate functions genSm = AST.GenerateSm label genScheme [] [compins] + +genZipWithCall :: + Entity + -> [CoreSyn.CoreBndr] + -> AST.GenerateSm +genZipWithCall entity [arg1, arg2, res] = genSm + where + -- Setup the generate scheme + len = (tfvec_len . Var.varType) res + label = mkVHDLExtId ("zipWithVector" ++ (varToString res)) + nPar = AST.unsafeVHDLBasicId "n" + range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1)) + genScheme = AST.ForGn nPar range + -- Get the entity name and port names + entity_id = ent_id entity + argports = map (Monad.liftM fst) (ent_args entity) + resport = (Monad.liftM fst) (ent_res entity) + -- Assign the ports + inport1 = mkAssocElemIndexed (argports!!0) (varToString arg1) nPar + inport2 = mkAssocElemIndexed (argports!!1) (varToString arg2) nPar + outport = mkAssocElemIndexed resport (varToString res) nPar + clk_port = mkAssocElem (Just $ mkVHDLExtId "clk") "clk" + portassigns = Maybe.catMaybes [inport1,inport2,outport,clk_port] + -- Generate the portmap + mapLabel = "zipWith" ++ (AST.fromVHDLId entity_id) + compins = mkComponentInst mapLabel entity_id portassigns + -- Return the generate functions + genSm = AST.GenerateSm label genScheme [] [compins] genUnconsVectorFuns :: AST.TypeMark -- ^ type of the vector elements -> AST.TypeMark -- ^ type of the vector @@ -74,7 +102,7 @@ genUnconsVectorFuns elemTM vectorTM = , AST.SubProgBody takeSpec [AST.SPVD takeVar] [takeExpr, takeRet] , AST.SubProgBody dropSpec [AST.SPVD dropVar] [dropExpr, dropRet] , AST.SubProgBody plusgtSpec [AST.SPVD plusgtVar] [plusgtExpr, plusgtRet] - , AST.SubProgBody emptySpec [AST.SPVD emptyVar] [emptyExpr] + , AST.SubProgBody emptySpec [AST.SPCD emptyVar] [emptyExpr] , AST.SubProgBody singletonSpec [AST.SPVD singletonVar] [singletonRet] , AST.SubProgBody copySpec [AST.SPVD copyVar] [copyExpr] ] @@ -217,12 +245,9 @@ genUnconsVectorFuns elemTM vectorTM = plusgtRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId) emptySpec = AST.Function emptyId [] vectorTM emptyVar = - AST.VarDec resId - (AST.SubtypeIn vectorTM - (Just $ AST.ConstraintIndex $ AST.IndexConstraint - [AST.ToRange (AST.PrimLit "0") - (AST.PrimLit "-1")])) - Nothing + AST.ConstDec resId + (AST.SubtypeIn vectorTM Nothing) + (Just $ AST.PrimLit "\"\"") emptyExpr = AST.ReturnSm (Just $ AST.PrimName (AST.NSimple resId)) singletonSpec = AST.Function singletonId [AST.IfaceVarDec aPar elemTM ] vectorTM