X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=FlattenTypes.hs;h=eba0599e271ce1245c5bf5549814a866d9d9be54;hb=221d523e2cd3de079ea642a65f31950caf94152b;hp=44879d00b6683d3c54d6965aab736984091c9e6a;hpb=ca2a895b27e5cc5a3e4b4da9e94efeb9779e1e79;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/FlattenTypes.hs b/FlattenTypes.hs
index 44879d0..eba0599 100644
--- a/FlattenTypes.hs
+++ b/FlattenTypes.hs
@@ -96,6 +96,12 @@ data SigDef =
     defDst :: SignalId
   } deriving (Show, Eq)
 
+-- | Is the given SigDef a FApp?
+is_FApp :: SigDef -> Bool
+is_FApp d = case d of  
+  (FApp _ _ _) -> True
+  _ -> False
+
 -- | An expression on signals
 data SignalExpr = 
   EqLit SignalId String -- ^ Is the given signal equal to the given (VHDL) literal
@@ -212,3 +218,5 @@ setSignalInfo id' info' = do
   (defs, sigs, n) <- State.get
   let sigs' = map (\(id, info) -> (id, if id == id' then info' else info)) sigs
   State.put (defs, sigs', n)
+
+-- vim: set ts=8 sw=2 sts=2 expandtab: