X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=FlattenTypes.hs;fp=FlattenTypes.hs;h=b7be4645d89e1df519487192268d48d4ab6e978c;hb=db63e913f56b427533d29327b25a14b6b75b6d79;hp=44879d00b6683d3c54d6965aab736984091c9e6a;hpb=0dd32af30fee665611e77cfb7bf8fc82f70c970b;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/FlattenTypes.hs b/FlattenTypes.hs
index 44879d0..b7be464 100644
--- a/FlattenTypes.hs
+++ b/FlattenTypes.hs
@@ -96,6 +96,12 @@ data SigDef =
     defDst :: SignalId
   } deriving (Show, Eq)
 
+-- | Is the given SigDef a FApp?
+is_FApp :: SigDef -> Bool
+is_FApp d = case d of  
+  (FApp _ _ _) -> True
+  _ -> False
+
 -- | An expression on signals
 data SignalExpr = 
   EqLit SignalId String -- ^ Is the given signal equal to the given (VHDL) literal