X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=Constants.hs;h=e9c4a4a2d6efc87c73f897db8910691606972727;hb=b8c1e8554ba8aee73bc9d9a54bb3cb32f7930957;hp=af8c324b300e2f52aae2ca36f8a42960e6fde837;hpb=c2f45d330f40225e7e5a1b6606665a16c2883d41;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/Constants.hs b/Constants.hs
index af8c324..e9c4a4a 100644
--- a/Constants.hs
+++ b/Constants.hs
@@ -1,6 +1,6 @@
 module Constants where
   
-import qualified ForSyDe.Backend.VHDL.AST as AST
+import qualified Language.VHDL.AST as AST
 
 --------------
 -- Identifiers
@@ -224,6 +224,43 @@ hwandId = "hwand"
 lengthTId :: String
 lengthTId = "lengthT"
 
+-- Numeric Operations
+
+-- | plus operation identifier
+plusId :: String
+plusId = "+"
+
+-- | times operation identifier
+timesId :: String
+timesId = "*"
+
+-- | negate operation identifier
+negateId :: String
+negateId = "negate"
+
+-- | minus operation identifier
+minusId :: String
+minusId = "-"
+
+-- | convert sizedword to ranged
+fromSizedWordId :: String
+fromSizedWordId = "fromSizedWord"
+
+toIntegerId :: String
+toIntegerId = "to_integer"
+
+fromIntegerId :: String
+fromIntegerId = "fromInteger"
+
+toSignedId :: String
+toSignedId = "to_signed"
+
+toUnsignedId :: String
+toUnsignedId = "to_unsigned"
+
+resizeId :: String
+resizeId = "resize"
+
 ------------------
 -- VHDL type marks
 ------------------
@@ -251,3 +288,11 @@ naturalTM = AST.unsafeVHDLBasicId "natural"
 -- | integer TypeMark
 integerTM :: AST.TypeMark
 integerTM = AST.unsafeVHDLBasicId "integer"
+
+-- | signed TypeMark
+signedTM :: AST.TypeMark
+signedTM = AST.unsafeVHDLBasicId "signed"
+
+-- | unsigned TypeMark
+unsignedTM :: AST.TypeMark
+unsignedTM = AST.unsafeVHDLBasicId "unsigned"