X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=Alu.hs;h=edb4d1a7440d63b9447ec7264fdc2595700cdd8a;hb=26fa82ed9c6c355343972ff1ca254b2cb4931b06;hp=0db8e7b6935517bc8ab264393cd40aaeab0538be;hpb=4a1b18cd81cebb66c95cc0ca8a6aaa441bee1418;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/Alu.hs b/Alu.hs
index 0db8e7b..edb4d1a 100644
--- a/Alu.hs
+++ b/Alu.hs
@@ -1,9 +1,6 @@
-module Alu  where
-import Bits
+module Alu where
 import qualified Sim
-import Data.SizedWord
-import Types
-import Types.Data.Num
+import CLasH.HardwareTypes hiding (fst,snd)
 import CLasH.Translator.Annotations
 import qualified Prelude as P
 
@@ -15,8 +12,6 @@ mainIO = Sim.simulateIO exec initial_state
 
 dontcare = Low
 
-newtype State s = State s deriving (P.Show)
-
 program = [
             -- (addr, we, op)
             (High, Low, High), -- z = r1 and t (0) ; t = r1 (1)
@@ -42,19 +37,21 @@ register_bank ::
   -> RegisterBankState -> -- State
   (RegisterBankState, Word) -- (State', Output)
 
-register_bank addr we d (State s) =
-  case we of
-    Low -> -- Read
-      let
-        o = case addr of Low -> fst s; High -> snd s
-      in (State s, o) -- Don't change state
-    High -> -- Write
-      let
-        (r0, r1) = s
-        r0' = case addr of Low -> d; High -> r0
-        r1' = case addr of High -> d; Low -> r1
-        s' = (r0', r1')
-      in (State s', 0) -- Don't output anything useful
+register_bank addr we d (State s) = (State s', o)
+  where
+    s' = case we of
+      Low -> s -- Read
+      High -> -- Write
+        let
+          (r0, r1) = s
+          r0' = case addr of Low -> d; High -> r0
+          r1' = case addr of High -> d; Low -> r1
+        in (r0', r1')
+    o = case we of
+      -- Read
+      Low -> case addr of Low -> fst s; High -> snd s
+      -- Write
+      High -> 0 -- Don't output anything useful
 
 -- ALU