X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=Alu.hs;h=ea9bae8cd551db729f16850f0146b7a756c64197;hb=0dd32af30fee665611e77cfb7bf8fc82f70c970b;hp=e9ddf5775869a4538ee064b120d0034e8730cf82;hpb=e771c40c12c3d93a1c59b396cf862cb0ac617d94;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/Alu.hs b/Alu.hs
index e9ddf57..ea9bae8 100644
--- a/Alu.hs
+++ b/Alu.hs
@@ -5,7 +5,7 @@ import qualified Sim
 main = Sim.simulate exec program initial_state
 mainIO = Sim.simulateIO exec initial_state
 
-dontcare = Low
+dontcare = DontCare
 
 program = [
             -- (addr, we, op)
@@ -43,8 +43,8 @@ register_bank (addr, High, d) s = -- Write
   where
     --Regs r0 r1 = s
     (r0, r1) = s
-    r0' = if addr == Low then d else r0
-    r1' = if addr == High then d else r1
+    r0' = case addr of Low -> d; High -> r0; otherwise -> dontcare
+    r1' = case addr of High -> d; Low -> r1; otherwise -> dontcare
     --s' = Regs r0' r1'
     s' = (r0', r1')
 
@@ -56,28 +56,16 @@ alu :: AluOp -> Bit -> Bit -> Bit
 alu High a b = a `hwand` b
 alu Low a b = a `hwor` b
 
-salu :: AluOp -> Bit -> Bit -> () -> ((), Bit)
-salu High a b s = (s, a `hwand` b)
-salu Low a b s = (s, a `hwor` b)
-
 type ExecState = (RegisterBankState, Bit, Bit)
-exec :: (RegAddr, Bit, AluOp) -> ExecState -> (ExecState, ())
+exec :: (RegAddr, Bit, AluOp) -> ExecState -> (ExecState, (Bit))
 
 -- Read & Exec
-exec (addr, Low, op) s =
-  (s', ())
+exec (addr, we, op) s =
+  (s', z')
   where
     (reg_s, t, z) = s
-    (reg_s', t') = register_bank (addr, Low, dontcare) reg_s
+    (reg_s', t') = register_bank (addr, we, z) reg_s
     z' = alu op t' t
     s' = (reg_s', t', z')
 
--- Write
-exec (addr, High, op) s =
-  (s', ())
-  where
-    (reg_s, t, z) = s
-    (reg_s', _) = register_bank (addr, High, z) reg_s
-    s' = (reg_s', t, z)
-
 -- vim: set ts=8 sw=2 sts=2 expandtab: