X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=Alu.hs;h=e9ddf5775869a4538ee064b120d0034e8730cf82;hb=e771c40c12c3d93a1c59b396cf862cb0ac617d94;hp=2495df25f0c80b885f4095012088e4f2b30f2623;hpb=d49dfd213e2cd384bceb38dc70eb122711d4f996;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/Alu.hs b/Alu.hs
index 2495df2..e9ddf57 100644
--- a/Alu.hs
+++ b/Alu.hs
@@ -1,70 +1,83 @@
-module Alu (main) where
+module Alu  where
 import Bits
 import qualified Sim
 
 main = Sim.simulate exec program initial_state
 mainIO = Sim.simulateIO exec initial_state
 
+dontcare = Low
+
 program = [
             -- (addr, we, op)
             (High, Low, High), -- z = r1 and t (0) ; t = r1 (1)
             (Low, Low, Low), -- z = r0 or t (1); t = r0 (0)
-            (Low, High, DontCare), -- r0 = z (1)
+            (Low, High, dontcare), -- r0 = z (1)
             (High, Low, High), -- z = r1 and t (0); t = r1 (1)
-            (High, High, DontCare) -- r1 = z (0)
+            (High, High, dontcare) -- r1 = z (0)
           ]
 
-initial_state = ((Low, High), (), Low, Low)
+--initial_state = (Regs Low High, Low, Low)
+initial_state = ((Low, High), Low, Low)
 
---
---
+-- Register bank
 
 type RegAddr = Bit
 type RegisterBankState = (Bit, Bit)
+--data RegisterBankState = Regs { r0, r1 :: Bit} deriving (Show)
+
 register_bank :: 
   (RegAddr, Bit, Bit) -> -- (addr, we, d)
   RegisterBankState -> -- s
   (RegisterBankState, Bit) -- (s', o)
 
 register_bank (Low, Low, _) s = -- Read r0
+  --(s, r0 s)
   (s, fst s)
 
 register_bank (High, Low, _) s = -- Read r1
+  --(s, r1 s)
   (s, snd s)
 
 register_bank (addr, High, d) s = -- Write
-  (s', DontCare)
+  (s', dontcare)
   where
+    --Regs r0 r1 = s
     (r0, r1) = s
     r0' = if addr == Low then d else r0
     r1' = if addr == High then d else r1
+    --s' = Regs r0' r1'
     s' = (r0', r1')
 
-type AluState = ()
+-- ALU
+
 type AluOp = Bit
 
-alu :: (AluOp, Bit, Bit) -> AluState -> (AluState, Bit)
-alu (High, a, b) s = ((), a `hwand` b)
-alu (Low, a, b) s = ((), a `hwor` b)
+alu :: AluOp -> Bit -> Bit -> Bit
+alu High a b = a `hwand` b
+alu Low a b = a `hwor` b
+
+salu :: AluOp -> Bit -> Bit -> () -> ((), Bit)
+salu High a b s = (s, a `hwand` b)
+salu Low a b s = (s, a `hwor` b)
 
-type ExecState = (RegisterBankState, AluState, Bit, Bit)
+type ExecState = (RegisterBankState, Bit, Bit)
 exec :: (RegAddr, Bit, AluOp) -> ExecState -> (ExecState, ())
 
 -- Read & Exec
 exec (addr, Low, op) s =
   (s', ())
   where
-    (reg_s, alu_s, t, z) = s
-    (reg_s', t') = register_bank (addr, Low, DontCare) reg_s
-    (alu_s', z') = alu (op, t', t) alu_s
-    s' = (reg_s', alu_s', t', z')
+    (reg_s, t, z) = s
+    (reg_s', t') = register_bank (addr, Low, dontcare) reg_s
+    z' = alu op t' t
+    s' = (reg_s', t', z')
 
 -- Write
 exec (addr, High, op) s =
   (s', ())
   where
-    (reg_s, alu_s, t, z) = s
+    (reg_s, t, z) = s
     (reg_s', _) = register_bank (addr, High, z) reg_s
-    s' = (reg_s', alu_s, t, z)
+    s' = (reg_s', t, z)
 
 -- vim: set ts=8 sw=2 sts=2 expandtab: