X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=Alu.hs;h=b3d5b220f13970bc123ccafd776dab62ffa483dd;hb=c46bdd4565d8c59c9c7a75ff1d08fdd47be19754;hp=17978204628b47ae06953944a9fbffd49c08205f;hpb=8ebcc3ed9b394000ccd07ffeb541f791444dfbc2;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/Alu.hs b/Alu.hs
index 1797820..b3d5b22 100644
--- a/Alu.hs
+++ b/Alu.hs
@@ -2,7 +2,7 @@ module Alu  where
 import Bits
 import qualified Sim
 import Data.SizedWord
-import Types.Data.Num
+import Types
 
 main = Sim.simulate exec program initial_state
 mainIO = Sim.simulateIO exec initial_state
@@ -58,8 +58,8 @@ alu :: AluOp -> Word -> Word -> Word
 {-# NOINLINE alu #-}
 --alu High a b = a `hwand` b
 --alu Low a b = a `hwor` b
-alu High a b = a
-alu Low a b = b
+alu High a b = a + b
+alu Low a b = a - b
 
 type ExecState = (RegisterBankState, Word, Word)
 exec :: (RegAddr, Bit, AluOp) -> ExecState -> (ExecState, Word)