X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=Alu.hs;h=adc350f06dff902d2dc8250191f7c692270aa4e5;hb=ee868ded42dccf7679190420e8d348aa8d727b98;hp=ea9bae8cd551db729f16850f0146b7a756c64197;hpb=56b4b2edb9bd1d06cafefc12a06feb7ef5622291;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/Alu.hs b/Alu.hs
index ea9bae8..adc350f 100644
--- a/Alu.hs
+++ b/Alu.hs
@@ -5,7 +5,7 @@ import qualified Sim
 main = Sim.simulate exec program initial_state
 mainIO = Sim.simulateIO exec initial_state
 
-dontcare = DontCare
+dontcare = Low
 
 program = [
             -- (addr, we, op)
@@ -43,8 +43,8 @@ register_bank (addr, High, d) s = -- Write
   where
     --Regs r0 r1 = s
     (r0, r1) = s
-    r0' = case addr of Low -> d; High -> r0; otherwise -> dontcare
-    r1' = case addr of High -> d; Low -> r1; otherwise -> dontcare
+    r0' = case addr of Low -> d; High -> r0
+    r1' = case addr of High -> d; Low -> r1
     --s' = Regs r0' r1'
     s' = (r0', r1')
 
@@ -53,6 +53,7 @@ register_bank (addr, High, d) s = -- Write
 type AluOp = Bit
 
 alu :: AluOp -> Bit -> Bit -> Bit
+{-# NOINLINE alu #-}
 alu High a b = a `hwand` b
 alu Low a b = a `hwor` b