X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=Alu.hs;h=40f76220ade83a2116b6f0bb928e8853cff34863;hb=dcf9dd6d86a5f256c1129146a977620ab6d8d466;hp=2495df25f0c80b885f4095012088e4f2b30f2623;hpb=d49dfd213e2cd384bceb38dc70eb122711d4f996;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/Alu.hs b/Alu.hs
index 2495df2..40f7622 100644
--- a/Alu.hs
+++ b/Alu.hs
@@ -14,31 +14,34 @@ program = [
             (High, High, DontCare) -- r1 = z (0)
           ]
 
-initial_state = ((Low, High), (), Low, Low)
+initial_state = (Regs Low High, (), Low, Low)
 
---
---
+-- Register bank
 
 type RegAddr = Bit
-type RegisterBankState = (Bit, Bit)
+--type RegisterBankState = (Bit, Bit)
+data RegisterBankState = Regs { r0, r1 :: Bit} deriving (Show)
+
 register_bank :: 
   (RegAddr, Bit, Bit) -> -- (addr, we, d)
   RegisterBankState -> -- s
   (RegisterBankState, Bit) -- (s', o)
 
 register_bank (Low, Low, _) s = -- Read r0
-  (s, fst s)
+  (s, r0 s)
 
 register_bank (High, Low, _) s = -- Read r1
-  (s, snd s)
+  (s, r1 s)
 
 register_bank (addr, High, d) s = -- Write
   (s', DontCare)
   where
-    (r0, r1) = s
+    Regs r0 r1 = s
     r0' = if addr == Low then d else r0
     r1' = if addr == High then d else r1
-    s' = (r0', r1')
+    s' = Regs r0' r1'
+
+-- ALU
 
 type AluState = ()
 type AluOp = Bit