X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=Alu.hs;h=3880245ff0d82a8ecee0609575a925903b90e3c1;hb=9b7d00ad53acfc821840051ef693d87470b4462b;hp=e9ddf5775869a4538ee064b120d0034e8730cf82;hpb=6b3da07384004751bc64ef88429f452dfe1cee45;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/Alu.hs b/Alu.hs
index e9ddf57..3880245 100644
--- a/Alu.hs
+++ b/Alu.hs
@@ -5,7 +5,7 @@ import qualified Sim
 main = Sim.simulate exec program initial_state
 mainIO = Sim.simulateIO exec initial_state
 
-dontcare = Low
+dontcare = DontCare
 
 program = [
             -- (addr, we, op)
@@ -43,8 +43,8 @@ register_bank (addr, High, d) s = -- Write
   where
     --Regs r0 r1 = s
     (r0, r1) = s
-    r0' = if addr == Low then d else r0
-    r1' = if addr == High then d else r1
+    r0' = case addr of Low -> d; High -> r0; otherwise -> dontcare
+    r1' = case addr of High -> d; Low -> r1; otherwise -> dontcare
     --s' = Regs r0' r1'
     s' = (r0', r1')