X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=Alu.hs;h=3880245ff0d82a8ecee0609575a925903b90e3c1;hb=9b7d00ad53acfc821840051ef693d87470b4462b;hp=07c0d0dfb076b46e0725ad4400698b12f41a616f;hpb=5d25b51d5dd6749a1b9ec06196a597f72e60782f;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/Alu.hs b/Alu.hs
index 07c0d0d..3880245 100644
--- a/Alu.hs
+++ b/Alu.hs
@@ -5,22 +5,25 @@ import qualified Sim
 main = Sim.simulate exec program initial_state
 mainIO = Sim.simulateIO exec initial_state
 
+dontcare = DontCare
+
 program = [
             -- (addr, we, op)
             (High, Low, High), -- z = r1 and t (0) ; t = r1 (1)
             (Low, Low, Low), -- z = r0 or t (1); t = r0 (0)
-            (Low, High, DontCare), -- r0 = z (1)
+            (Low, High, dontcare), -- r0 = z (1)
             (High, Low, High), -- z = r1 and t (0); t = r1 (1)
-            (High, High, DontCare) -- r1 = z (0)
+            (High, High, dontcare) -- r1 = z (0)
           ]
 
-initial_state = (Regs Low High, Low, Low)
+--initial_state = (Regs Low High, Low, Low)
+initial_state = ((Low, High), Low, Low)
 
 -- Register bank
 
 type RegAddr = Bit
---type RegisterBankState = (Bit, Bit)
-data RegisterBankState = Regs { r0, r1 :: Bit} deriving (Show)
+type RegisterBankState = (Bit, Bit)
+--data RegisterBankState = Regs { r0, r1 :: Bit} deriving (Show)
 
 register_bank :: 
   (RegAddr, Bit, Bit) -> -- (addr, we, d)
@@ -28,18 +31,22 @@ register_bank ::
   (RegisterBankState, Bit) -- (s', o)
 
 register_bank (Low, Low, _) s = -- Read r0
-  (s, r0 s)
+  --(s, r0 s)
+  (s, fst s)
 
 register_bank (High, Low, _) s = -- Read r1
-  (s, r1 s)
+  --(s, r1 s)
+  (s, snd s)
 
 register_bank (addr, High, d) s = -- Write
-  (s', DontCare)
+  (s', dontcare)
   where
-    Regs r0 r1 = s
-    r0' = if addr == Low then d else r0
-    r1' = if addr == High then d else r1
-    s' = Regs r0' r1'
+    --Regs r0 r1 = s
+    (r0, r1) = s
+    r0' = case addr of Low -> d; High -> r0; otherwise -> dontcare
+    r1' = case addr of High -> d; Low -> r1; otherwise -> dontcare
+    --s' = Regs r0' r1'
+    s' = (r0', r1')
 
 -- ALU
 
@@ -49,6 +56,10 @@ alu :: AluOp -> Bit -> Bit -> Bit
 alu High a b = a `hwand` b
 alu Low a b = a `hwor` b
 
+salu :: AluOp -> Bit -> Bit -> () -> ((), Bit)
+salu High a b s = (s, a `hwand` b)
+salu Low a b s = (s, a `hwor` b)
+
 type ExecState = (RegisterBankState, Bit, Bit)
 exec :: (RegAddr, Bit, AluOp) -> ExecState -> (ExecState, ())
 
@@ -57,7 +68,7 @@ exec (addr, Low, op) s =
   (s', ())
   where
     (reg_s, t, z) = s
-    (reg_s', t') = register_bank (addr, Low, DontCare) reg_s
+    (reg_s', t') = register_bank (addr, Low, dontcare) reg_s
     z' = alu op t' t
     s' = (reg_s', t', z')