X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=Alu.hs;h=17978204628b47ae06953944a9fbffd49c08205f;hb=8ebcc3ed9b394000ccd07ffeb541f791444dfbc2;hp=3880245ff0d82a8ecee0609575a925903b90e3c1;hpb=9b7d00ad53acfc821840051ef693d87470b4462b;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/Alu.hs b/Alu.hs
index 3880245..1797820 100644
--- a/Alu.hs
+++ b/Alu.hs
@@ -1,11 +1,13 @@
 module Alu  where
 import Bits
 import qualified Sim
+import Data.SizedWord
+import Types.Data.Num
 
 main = Sim.simulate exec program initial_state
 mainIO = Sim.simulateIO exec initial_state
 
-dontcare = DontCare
+dontcare = Low
 
 program = [
             -- (addr, we, op)
@@ -17,18 +19,18 @@ program = [
           ]
 
 --initial_state = (Regs Low High, Low, Low)
-initial_state = ((Low, High), Low, Low)
+initial_state = ((0, 1), 0, 0)
 
+type Word = SizedWord D4
 -- Register bank
-
 type RegAddr = Bit
-type RegisterBankState = (Bit, Bit)
+type RegisterBankState = (Word, Word)
 --data RegisterBankState = Regs { r0, r1 :: Bit} deriving (Show)
 
 register_bank :: 
-  (RegAddr, Bit, Bit) -> -- (addr, we, d)
+  (RegAddr, Bit, Word) -> -- (addr, we, d)
   RegisterBankState -> -- s
-  (RegisterBankState, Bit) -- (s', o)
+  (RegisterBankState, Word) -- (s', o)
 
 register_bank (Low, Low, _) s = -- Read r0
   --(s, r0 s)
@@ -39,12 +41,12 @@ register_bank (High, Low, _) s = -- Read r1
   (s, snd s)
 
 register_bank (addr, High, d) s = -- Write
-  (s', dontcare)
+  (s', 0)
   where
     --Regs r0 r1 = s
     (r0, r1) = s
-    r0' = case addr of Low -> d; High -> r0; otherwise -> dontcare
-    r1' = case addr of High -> d; Low -> r1; otherwise -> dontcare
+    r0' = case addr of Low -> d; High -> r0
+    r1' = case addr of High -> d; Low -> r1
     --s' = Regs r0' r1'
     s' = (r0', r1')
 
@@ -52,32 +54,23 @@ register_bank (addr, High, d) s = -- Write
 
 type AluOp = Bit
 
-alu :: AluOp -> Bit -> Bit -> Bit
-alu High a b = a `hwand` b
-alu Low a b = a `hwor` b
-
-salu :: AluOp -> Bit -> Bit -> () -> ((), Bit)
-salu High a b s = (s, a `hwand` b)
-salu Low a b s = (s, a `hwor` b)
+alu :: AluOp -> Word -> Word -> Word
+{-# NOINLINE alu #-}
+--alu High a b = a `hwand` b
+--alu Low a b = a `hwor` b
+alu High a b = a
+alu Low a b = b
 
-type ExecState = (RegisterBankState, Bit, Bit)
-exec :: (RegAddr, Bit, AluOp) -> ExecState -> (ExecState, ())
+type ExecState = (RegisterBankState, Word, Word)
+exec :: (RegAddr, Bit, AluOp) -> ExecState -> (ExecState, Word)
 
 -- Read & Exec
-exec (addr, Low, op) s =
-  (s', ())
+exec (addr, we, op) s =
+  (s', z')
   where
     (reg_s, t, z) = s
-    (reg_s', t') = register_bank (addr, Low, dontcare) reg_s
+    (reg_s', t') = register_bank (addr, we, z) reg_s
     z' = alu op t' t
     s' = (reg_s', t', z')
 
--- Write
-exec (addr, High, op) s =
-  (s', ())
-  where
-    (reg_s, t, z) = s
-    (reg_s', _) = register_bank (addr, High, z) reg_s
-    s' = (reg_s', t, z)
-
 -- vim: set ts=8 sw=2 sts=2 expandtab: