X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=Alu.hs;h=07c0d0dfb076b46e0725ad4400698b12f41a616f;hb=5d25b51d5dd6749a1b9ec06196a597f72e60782f;hp=b888fc9dca18419523a4b33234c6e8e900d083ac;hpb=4cc22e06d666e970b6bea28c6fb43c4c3f7fd834;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/Alu.hs b/Alu.hs
index b888fc9..07c0d0d 100644
--- a/Alu.hs
+++ b/Alu.hs
@@ -1,4 +1,4 @@
-module Alu (main) where
+module Alu  where
 import Bits
 import qualified Sim
 
@@ -45,9 +45,9 @@ register_bank (addr, High, d) s = -- Write
 
 type AluOp = Bit
 
-alu :: (AluOp, Bit, Bit) -> Bit
-alu (High, a, b) = a `hwand` b
-alu (Low, a, b) = a `hwor` b
+alu :: AluOp -> Bit -> Bit -> Bit
+alu High a b = a `hwand` b
+alu Low a b = a `hwor` b
 
 type ExecState = (RegisterBankState, Bit, Bit)
 exec :: (RegAddr, Bit, AluOp) -> ExecState -> (ExecState, ())
@@ -58,7 +58,7 @@ exec (addr, Low, op) s =
   where
     (reg_s, t, z) = s
     (reg_s', t') = register_bank (addr, Low, DontCare) reg_s
-    z' = alu (op, t', t)
+    z' = alu op t' t
     s' = (reg_s', t', z')
 
 -- Write