X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=Alu.hs;fp=Alu.hs;h=0fba3406d9bf55dfb532f93d46144adf58c988cc;hb=2ee391fd9b32f39872abfcf339e949f5139c6cbd;hp=ea9bae8cd551db729f16850f0146b7a756c64197;hpb=d5cfe79d359fd4d7177a6cc7232ccb294ce039f8;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/Alu.hs b/Alu.hs
index ea9bae8..0fba340 100644
--- a/Alu.hs
+++ b/Alu.hs
@@ -5,7 +5,7 @@ import qualified Sim
 main = Sim.simulate exec program initial_state
 mainIO = Sim.simulateIO exec initial_state
 
-dontcare = DontCare
+dontcare = Low
 
 program = [
             -- (addr, we, op)
@@ -43,8 +43,8 @@ register_bank (addr, High, d) s = -- Write
   where
     --Regs r0 r1 = s
     (r0, r1) = s
-    r0' = case addr of Low -> d; High -> r0; otherwise -> dontcare
-    r1' = case addr of High -> d; Low -> r1; otherwise -> dontcare
+    r0' = case addr of Low -> d; High -> r0
+    r1' = case addr of High -> d; Low -> r1
     --s' = Regs r0' r1'
     s' = (r0', r1')