X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=Adders.hs;h=f07c8e9acf673338be33ba4df7ea6ed23d9e8808;hb=8ebcc3ed9b394000ccd07ffeb541f791444dfbc2;hp=b09b98fdc4b43823fc13325f9887a7ea7f6cf260;hpb=c31e721d3b194f19140ffb55fdfc8d00368a6dbd;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/Adders.hs b/Adders.hs
index b09b98f..f07c8e9 100644
--- a/Adders.hs
+++ b/Adders.hs
@@ -2,11 +2,14 @@ module Adders where
 import Bits
 import qualified Sim
 import Language.Haskell.Syntax
+import Data.TypeLevel
+import qualified Data.Param.FSVec as FSVec
 
 mainIO f = Sim.simulateIO (Sim.stateless f) ()
 
 -- This function is from Sim.hs, but we redefine it here so it can get inlined
 -- by default.
+stateless :: (i -> o) -> (i -> () -> ((), o))
 stateless f = \i s -> (s, f i)
 
 show_add f = do print ("Sum:   " ++ (displaysigs s)); print ("Carry: " ++ (displaysig c))
@@ -15,10 +18,39 @@ show_add f = do print ("Sum:   " ++ (displaysigs s)); print ("Carry: " ++ (displ
     b = [Low, Low, Low, High]
     (s, c) = f (a, b)
 
+mux2 :: Bit -> (Bit, Bit) -> Bit
+mux2 Low (a, b) = a
+mux2 High (a, b) = b
+
 -- Not really an adder, but this is nice minimal hardware description
 wire :: Bit -> Bit
 wire a = a
 
+bus :: (Pos len) => BitVec len -> BitVec len
+bus v = v
+
+bus_4 :: BitVec D4 -> BitVec D4
+bus_4 v = v
+
+{-
+inv_n :: (Pos len) => BitVec len -> BitVec len
+inv_n v =
+  --FSVec.map hwnot v
+  inv_n_rec v
+
+class Inv vec where
+  inv_n_rec :: vec -> vec
+
+instance (Pos len) => Inv (BitVec len) where
+  inv_n_rec v = 
+    h FSVec.+> t
+    where
+      h = FSVec.head v
+      t = FSVec.tail v
+
+instance Inv (BitVec D0) where
+  inv_n_rec v = v
+-}
 -- Not really an adder either, but a slightly more complex example
 inv :: Bit -> Bit
 inv a = hwnot a
@@ -31,6 +63,21 @@ invinv a = hwnot (hwnot a)
 dup :: Bit -> (Bit, Bit)
 dup a = (a, a)
 
+-- Not really an adder either, but a simple stateful example (D-flipflop)
+dff :: Bit -> Bit -> (Bit, Bit)
+dff d s = (s', q)
+  where
+    q = s
+    s' = d
+
+type ShifterState = (Bit, Bit, Bit, Bit)
+shifter :: Bit -> ShifterState -> (ShifterState, Bit)
+shifter a s =
+  (s', o)
+  where
+    s' = (a, b, c, d)
+    (b, c, d, o) = s
+
 -- Combinatoric stateless no-carry adder
 -- A -> B -> S
 no_carry_adder :: (Bit, Bit) -> Bit
@@ -39,6 +86,7 @@ no_carry_adder (a, b) = a `hwxor` b
 -- Combinatoric stateless half adder
 -- A -> B -> (S, C)
 half_adder :: (Bit, Bit) -> (Bit, Bit)
+{-# NOINLINE half_adder #-}
 half_adder (a, b) = 
   ( a `hwxor` b, a `hwand` b )