X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=Adders.hs;h=b09b98fdc4b43823fc13325f9887a7ea7f6cf260;hb=296146a80304f2763e7bc0d7d4f7cbe63036937b;hp=71d38dc4197293febaaca3917998fc8cf94841e2;hpb=1e7d79de8b34aca4bf0f63d3822dd0b018356038;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/Adders.hs b/Adders.hs
index 71d38dc..b09b98f 100644
--- a/Adders.hs
+++ b/Adders.hs
@@ -1,8 +1,13 @@
 module Adders where
 import Bits
+import qualified Sim
 import Language.Haskell.Syntax
 
-main = do show_add exp_adder; show_add rec_adder;
+mainIO f = Sim.simulateIO (Sim.stateless f) ()
+
+-- This function is from Sim.hs, but we redefine it here so it can get inlined
+-- by default.
+stateless f = \i s -> (s, f i)
 
 show_add f = do print ("Sum:   " ++ (displaysigs s)); print ("Carry: " ++ (displaysig c))
   where
@@ -42,9 +47,11 @@ half_adder (a, b) =
 full_adder :: (Bit, Bit, Bit) -> (Bit, Bit)
 full_adder (a, b, cin) = (s, c)
   where
-    x = a `hwxor` b
-    s = x `hwxor` cin
-    c = a `hwand` b `hwor` (cin `hwand` x)
+    (s1, c1) = half_adder(a, b)
+    (s, c2)  = half_adder(s1, cin)
+    c        = c1 `hwor` c2
+
+sfull_adder = stateless full_adder
 
 -- Four bit adder
 -- Explicit version