X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=Adders.hs;h=2ee1de69534f144ab6f41d627fdfc7ce950e4f05;hb=e230d86ae7135a268a72cdffba947a9011001ec2;hp=c2810d5b397af025816fa3e0ed5a87e95163ab0d;hpb=3030ecf26661130e26135edd04723bd771bec626;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git diff --git a/Adders.hs b/Adders.hs index c2810d5..2ee1de6 100644 --- a/Adders.hs +++ b/Adders.hs @@ -1,8 +1,16 @@ module Adders where import Bits +import qualified Sim import Language.Haskell.Syntax +import qualified Data.TypeLevel as TypeLevel +import qualified Data.Param.FSVec as FSVec -main = do show_add exp_adder; show_add rec_adder; +mainIO f = Sim.simulateIO (Sim.stateless f) () + +-- This function is from Sim.hs, but we redefine it here so it can get inlined +-- by default. +stateless :: (i -> o) -> (i -> () -> ((), o)) +stateless f = \i s -> (s, f i) show_add f = do print ("Sum: " ++ (displaysigs s)); print ("Carry: " ++ (displaysig c)) where @@ -10,13 +18,85 @@ show_add f = do print ("Sum: " ++ (displaysigs s)); print ("Carry: " ++ (displ b = [Low, Low, Low, High] (s, c) = f (a, b) +mux2 :: Bit -> (Bit, Bit) -> Bit +mux2 Low (a, b) = a +mux2 High (a, b) = b + -- Not really an adder, but this is nice minimal hardware description wire :: Bit -> Bit wire a = a +bus :: (TypeLevel.Pos len) => BitVec len -> BitVec len +bus v = v + +bus_4 :: BitVec TypeLevel.D4 -> BitVec TypeLevel.D4 +bus_4 v = v + +{- +inv_n :: (Pos len) => BitVec len -> BitVec len +inv_n v = + --FSVec.map hwnot v + inv_n_rec v + +class Inv vec where + inv_n_rec :: vec -> vec + +instance (Pos len) => Inv (BitVec len) where + inv_n_rec v = + h FSVec.+> t + where + h = FSVec.head v + t = FSVec.tail v + +instance Inv (BitVec D0) where + inv_n_rec v = v +-} -- Not really an adder either, but a slightly more complex example inv :: Bit -> Bit -inv a = hwnot a +inv a = let r = hwnot a in r + +-- Not really an adder either, but a slightly more complex example +invinv :: Bit -> Bit +invinv a = hwnot (hwnot a) + +-- Not really an adder either, but a slightly more complex example +dup :: Bit -> (Bit, Bit) +dup a = (a, a) + +-- Not really an adder either, but a simple stateful example (D-flipflop) +dff :: Bit -> Bit -> (Bit, Bit) +dff d s = (s', q) + where + q = s + s' = d + +type ShifterState = (Bit, Bit, Bit, Bit) +shifter :: Bit -> ShifterState -> (ShifterState, Bit) +shifter i (a, b, c, d) = + (s', d) + where + s' = (i, a, b, c) + +{-# NOINLINE shifter_en #-} +shifter_en :: Bit -> Bit-> ShifterState -> (ShifterState, Bit) +shifter_en High i (a, b, c, d) = + (s', d) + where + s' = (i, a, b, c) + +shifter_en Low i s@(a, b, c, d) = + (s, d) + +-- Two multiplexed shifters +type ShiftersState = (ShifterState, ShifterState) +shifters :: Bit -> Bit -> ShiftersState -> (ShiftersState, Bit) +shifters sel i (sa, sb) = + (s', out) + where + (sa', outa) = shifter_en sel i sa + (sb', outb) = shifter_en (hwnot sel) i sb + s' = (sa', sb') + out = if sel == High then outa else outb -- Combinatoric stateless no-carry adder -- A -> B -> S @@ -26,6 +106,7 @@ no_carry_adder (a, b) = a `hwxor` b -- Combinatoric stateless half adder -- A -> B -> (S, C) half_adder :: (Bit, Bit) -> (Bit, Bit) +{-# NOINLINE half_adder #-} half_adder (a, b) = ( a `hwxor` b, a `hwand` b ) @@ -34,8 +115,11 @@ half_adder (a, b) = full_adder :: (Bit, Bit, Bit) -> (Bit, Bit) full_adder (a, b, cin) = (s, c) where - s = a `hwxor` b `hwxor` cin - c = a `hwand` b `hwor` (cin `hwand` (a `hwxor` b)) + (s1, c1) = half_adder(a, b) + (s, c2) = half_adder(s1, cin) + c = c1 `hwor` c2 + +sfull_adder = stateless full_adder -- Four bit adder -- Explicit version @@ -62,6 +146,25 @@ rec_adder ((a:as), (b:bs)) = (rest, cin) = rec_adder (as, bs) (s, cout) = full_adder (a, b, cin) +foo = id +add, sub :: Int -> Int -> Int +add a b = a + b +sub a b = a - b + +highordtest = \x -> + let s = foo x + in + case s of + (a, b) -> + case a of + High -> add + Low -> let + op' = case b of + High -> sub + Low -> \c d -> c + in + \c d -> op' d c + -- Four bit adder, using the continous adder below -- [a] -> [b] -> ([s], cout) --con_adder_4 as bs =