X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;f=Adders.hs;h=249bb3a4ef983a84f7f3074f131934688b2974b3;hb=3f12ee5d723fd8c01190c5971641141a8c7a9d98;hp=f32f5d4f9fd89acaa71d4535c072dafeb5f78361;hpb=c13ec403850827c4679eb6979476a3876f96a397;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/Adders.hs b/Adders.hs
index f32f5d4..249bb3a 100644
--- a/Adders.hs
+++ b/Adders.hs
@@ -2,22 +2,58 @@ module Adders where
 import Bits
 import qualified Sim
 import Language.Haskell.Syntax
+import qualified Data.TypeLevel as TypeLevel
+import qualified Data.Param.FSVec as FSVec
 
 mainIO f = Sim.simulateIO (Sim.stateless f) ()
 
+-- This function is from Sim.hs, but we redefine it here so it can get inlined
+-- by default.
+stateless :: (i -> o) -> (i -> () -> ((), o))
+stateless f = \i s -> (s, f i)
+
 show_add f = do print ("Sum:   " ++ (displaysigs s)); print ("Carry: " ++ (displaysig c))
   where
     a = [High, High, High, High]
     b = [Low, Low, Low, High]
     (s, c) = f (a, b)
 
+mux2 :: Bit -> (Bit, Bit) -> Bit
+mux2 Low (a, b) = a
+mux2 High (a, b) = b
+
 -- Not really an adder, but this is nice minimal hardware description
 wire :: Bit -> Bit
 wire a = a
 
+bus :: (TypeLevel.Pos len) => BitVec len -> BitVec len
+bus v = v
+
+bus_4 :: BitVec TypeLevel.D4 -> BitVec TypeLevel.D4
+bus_4 v = v
+
+{-
+inv_n :: (Pos len) => BitVec len -> BitVec len
+inv_n v =
+  --FSVec.map hwnot v
+  inv_n_rec v
+
+class Inv vec where
+  inv_n_rec :: vec -> vec
+
+instance (Pos len) => Inv (BitVec len) where
+  inv_n_rec v = 
+    h FSVec.+> t
+    where
+      h = FSVec.head v
+      t = FSVec.tail v
+
+instance Inv (BitVec D0) where
+  inv_n_rec v = v
+-}
 -- Not really an adder either, but a slightly more complex example
 inv :: Bit -> Bit
-inv a = hwnot a
+inv a = let r = hwnot a in r
 
 -- Not really an adder either, but a slightly more complex example
 invinv :: Bit -> Bit
@@ -27,6 +63,41 @@ invinv a = hwnot (hwnot a)
 dup :: Bit -> (Bit, Bit)
 dup a = (a, a)
 
+-- Not really an adder either, but a simple stateful example (D-flipflop)
+dff :: Bit -> Bit -> (Bit, Bit)
+dff d s = (s', q)
+  where
+    q = s
+    s' = d
+
+type ShifterState = (Bit, Bit, Bit, Bit)
+shifter :: Bit -> ShifterState -> (ShifterState, Bit)
+shifter i (a, b, c, d) =
+  (s', d)
+  where
+    s' = (i, a, b, c)
+
+{-# NOINLINE shifter_en #-}
+shifter_en :: Bit -> Bit-> ShifterState -> (ShifterState, Bit)
+shifter_en High i (a, b, c, d) =
+  (s', d)
+  where
+    s' = (i, a, b, c)
+
+shifter_en Low i s@(a, b, c, d) =
+  (s, d)
+
+-- Two multiplexed shifters
+type ShiftersState = (ShifterState, ShifterState)
+shifters :: Bit -> Bit -> ShiftersState -> (ShiftersState, Bit)
+shifters sel i (sa, sb) =
+  (s', out)
+  where
+    (sa', outa) = shifter_en sel i sa
+    (sb', outb) = shifter_en (hwnot sel) i sb
+    s' = (sa', sb')
+    out = if sel == High then outa else outb
+
 -- Combinatoric stateless no-carry adder
 -- A -> B -> S
 no_carry_adder :: (Bit, Bit) -> Bit
@@ -35,6 +106,7 @@ no_carry_adder (a, b) = a `hwxor` b
 -- Combinatoric stateless half adder
 -- A -> B -> (S, C)
 half_adder :: (Bit, Bit) -> (Bit, Bit)
+{-# NOINLINE half_adder #-}
 half_adder (a, b) = 
   ( a `hwxor` b, a `hwand` b )
 
@@ -47,6 +119,8 @@ full_adder (a, b, cin) = (s, c)
     (s, c2)  = half_adder(s1, cin)
     c        = c1 `hwor` c2
 
+sfull_adder = stateless full_adder
+
 -- Four bit adder
 -- Explicit version
 -- [a] -> [b] -> ([s], cout)