X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;ds=sidebyside;f=c%CE%BBash%2FCLasH%2FVHDL%2FGenerate.hs;h=d92b9ae96f4b3f3379862275c9081b19bc77f5a0;hb=d699d2f50e6d172308ef56adec01ace357ef0a0f;hp=3f81f8f12c9b52e0b2d3641d36ed546663849dfe;hpb=575a772a99af0b2b169b83c83b21a2bf07798bd2;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git "a/c\316\273ash/CLasH/VHDL/Generate.hs" "b/c\316\273ash/CLasH/VHDL/Generate.hs"
index 3f81f8f..d92b9ae 100644
--- "a/c\316\273ash/CLasH/VHDL/Generate.hs"
+++ "b/c\316\273ash/CLasH/VHDL/Generate.hs"
@@ -1376,6 +1376,7 @@ globalNameTable = Map.fromList
   , (hwandId          , (2, genOperator2 AST.And    ) )
   , (hworId           , (2, genOperator2 AST.Or     ) )
   , (hwnotId          , (1, genOperator1 AST.Not    ) )
+  , (equalsId         , (2, genOperator2 (AST.:=:)  ) )
   , (plusId           , (2, genOperator2 (AST.:+:)  ) )
   , (timesId          , (2, genOperator2 (AST.:*:)  ) )
   , (negateId         , (1, genNegation             ) )