X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;ds=sidebyside;f=VHDLTypes.hs;h=c1d9332f993d340772e2d7d9cfbb19a60187ab52;hb=1a10d214e6ffc7097c0f4bddf16f0dd87b5355a8;hp=3e2ebe09ffebc4c55493a34c8afe6792e9d19679;hpb=969b7ddd86b69d2fc61b101961affcca0364749c;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/VHDLTypes.hs b/VHDLTypes.hs
index 3e2ebe0..c1d9332 100644
--- a/VHDLTypes.hs
+++ b/VHDLTypes.hs
@@ -18,21 +18,17 @@ import qualified CoreSyn
 import qualified ForSyDe.Backend.VHDL.AST as AST
 
 -- Local imports
-import FlattenTypes
-import HsValueMap
 
-type VHDLSignalMapElement = (Maybe (AST.VHDLId, AST.TypeMark))
--- | A mapping from a haskell structure to the corresponding VHDL port
---   signature, or Nothing for values that do not translate to a port.
-type VHDLSignalMap = HsValueMap VHDLSignalMapElement
+-- A description of a port of an entity
+type Port = (AST.VHDLId, AST.TypeMark)
 
 -- A description of a VHDL entity. Contains both the entity itself as well as
 -- info on how to map a haskell value (argument / result) on to the entity's
 -- ports.
 data Entity = Entity { 
   ent_id     :: AST.VHDLId,           -- The id of the entity
-  ent_args   :: [VHDLSignalMapElement],      -- A mapping of each function argument to port names
-  ent_res    :: VHDLSignalMapElement         -- A mapping of the function result to port names
+  ent_args   :: [Port],      -- A mapping of each function argument to port names
+  ent_res    :: Port         -- A mapping of the function result to port names
 } deriving (Show);
 
 -- A orderable equivalent of CoreSyn's Type for use as a map key
@@ -45,9 +41,6 @@ instance Ord OrdType where
 -- A map of a Core type to the corresponding type name
 type TypeMap = Map.Map OrdType (AST.VHDLId, Either AST.TypeDef AST.SubtypeIn)
 
--- A map of Elem types to the corresponding VHDL Id for the Vector
-type ElemTypeMap = Map.Map OrdType (AST.VHDLId, AST.TypeDef)
-
 -- A map of a vector Core element type and function name to the coressponding
 -- VHDLId of the function and the function body.
 type TypeFunMap = Map.Map (OrdType, String) (AST.VHDLId, AST.SubProgBody)
@@ -58,8 +51,6 @@ type SignatureMap = Map.Map CoreSyn.CoreBndr Entity
 data VHDLState = VHDLState {
   -- | A map of Core type -> VHDL Type
   vsTypes_      :: TypeMap,
-  -- | A map of Elem types -> VHDL Vector Id
-  vsElemTypes_   :: ElemTypeMap,
   -- | A map of vector Core type -> VHDL type function
   vsTypeFuns_   :: TypeFunMap,
   -- | A map of HsFunction -> hardware signature (entity name, port names,