X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;ds=sidebyside;f=VHDL.hs;h=f1c7500ea032f1283d63735ba79aa348a0669a2c;hb=41e6a89a1d9347431e80b895cb74ab5ecc03e9b7;hp=ae7dfc9bfd42f360fa70f0beb8526770dfc5c01f;hpb=185b1f477826325e1076ec552a432335867e7b03;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/VHDL.hs b/VHDL.hs
index ae7dfc9..f1c7500 100644
--- a/VHDL.hs
+++ b/VHDL.hs
@@ -11,7 +11,6 @@ import qualified Maybe
 import Outputable ( showSDoc, ppr )
 import qualified ForSyDe.Backend.VHDL.AST as AST
 
-
 -- | The VHDL Bit type
 bit_ty :: AST.TypeMark
 bit_ty = AST.unsafeVHDLBasicId "Bit"