X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;ds=sidebyside;f=VHDL.hs;h=6b8b7b6d3ba26635ad94832659b9d41dc30615c9;hb=4e69cb591dcca330d8f2a8c2e09fa2026c8fc7f2;hp=9cea6fe74c333910ef8fd1b9919d61e8e5f9694f;hpb=7a5b4eb318626f327dd6b0d69e99a8247f56399c;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/VHDL.hs b/VHDL.hs
index 9cea6fe..6b8b7b6 100644
--- a/VHDL.hs
+++ b/VHDL.hs
@@ -33,15 +33,15 @@ createEntity hsfunc fdata =
     Just flatfunc ->
       
       let 
-        s       = sigs flatfunc
-        a       = args flatfunc
-        r       = res  flatfunc
-        args'   = map (fmap (mkMap s)) a
-        res'    = fmap (mkMap s) r
+        sigs    = flat_sigs flatfunc
+        args    = flat_args flatfunc
+        res     = flat_res  flatfunc
+        args'   = map (fmap (mkMap sigs)) args
+        res'    = fmap (mkMap sigs) res
         ent_decl' = createEntityAST hsfunc args' res'
         entity' = Entity args' res' (Just ent_decl')
       in
-        fdata { entity = Just entity' }
+        fdata { funcEntity = Just entity' }
   where
     mkMap :: Eq id => [(id, SignalInfo)] -> id -> (AST.VHDLId, AST.TypeMark)
     mkMap sigmap id =
@@ -99,14 +99,19 @@ createArchitecture hsfunc fdata =
     -- Create an architecture for all other functions
     Just flatfunc ->
       let 
-        s        = sigs flatfunc
-        a        = args flatfunc
-        r        = res  flatfunc
+        sigs      = flat_sigs flatfunc
+        args      = flat_args flatfunc
+        res       = flat_res  flatfunc
+        apps      = flat_apps flatfunc
         entity_id = Maybe.fromMaybe
                       (error $ "Building architecture without an entity? This should not happen!")
                       (getEntityId fdata)
-        sig_decs = [mkSigDec info | (id, info) <- s, (all (id `Foldable.notElem`) (r:a)) ]
-        arch     = AST.ArchBody (mkVHDLId "structural") (AST.NSimple entity_id) (map AST.BDISD sig_decs) []
+        -- Create signal declarations for all signals that are not in args and
+        -- res
+        sig_decs = [mkSigDec info | (id, info) <- sigs, (all (id `Foldable.notElem`) (res:args)) ]
+        -- Create component instantiations for all function applications
+        insts    = map (AST.CSISm . mkCompInsSm) apps
+        arch     = AST.ArchBody (mkVHDLId "structural") (AST.NSimple entity_id) (map AST.BDISD sig_decs) insts
       in
         fdata { funcArch = Just arch }
 
@@ -118,11 +123,23 @@ mkSigDec info =
       (error $ "Unnamed signal? This should not happen!")
       (sigName info)
     ty = sigTy info
-    
+
+-- | Transforms a flat function application to a VHDL component instantiation.
+mkCompInsSm ::
+  FApp UnnamedSignal  -- | The application to look at.
+  -> AST.CompInsSm    -- | The corresponding VHDL component instantiation.
+
+mkCompInsSm app =
+  AST.CompInsSm label (AST.IUEntity (AST.NSimple entity_id)) (AST.PMapAspect portmaps)
+  where
+    entity_id = mkVHDLId "foo"
+    label     = mkVHDLId "app"
+    portmaps  = []
+
 -- | Extracts the generated entity id from the given funcdata
 getEntityId :: FuncData -> Maybe AST.VHDLId
 getEntityId fdata =
-  case entity fdata of
+  case funcEntity fdata of
     Nothing -> Nothing
     Just e  -> case ent_decl e of
       Nothing -> Nothing
@@ -133,7 +150,7 @@ getLibraryUnits ::
   -> [AST.LibraryUnit]        -- | The library units it generates
 
 getLibraryUnits (hsfunc, fdata) =
-  case entity fdata of 
+  case funcEntity fdata of 
     Nothing -> []
     Just ent -> case ent_decl ent of
       Nothing -> []