X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;ds=sidebyside;f=Translator.hs;h=f377152c775c9deaf7b8efed06453a63403e7a3b;hb=c5bde4d7862c7df2b4bad183088f77a43d8b5a2c;hp=550b4f0800475b348d4a6146aa317527d74af79d;hpb=998e440a7fa765685e1ed500c871058a33129b1f;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/Translator.hs b/Translator.hs
index 550b4f0..f377152 100644
--- a/Translator.hs
+++ b/Translator.hs
@@ -58,7 +58,7 @@ makeVHDL filename name stateful = do
   -- Translate to VHDL
   vhdl <- moduleToVHDL core [(name, stateful)]
   -- Write VHDL to file
-  let dir = "../vhdl/vhdl/" ++ name ++ "/"
+  let dir = "./vhdl/" ++ name ++ "/"
   mapM (writeVHDL dir) vhdl
   return ()