X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;ds=sidebyside;f=Translator.hs;h=b4301a3f1a0b6c3451c0636025bce2a8a947900d;hb=185b1f477826325e1076ec552a432335867e7b03;hp=babd622fda8df41c8c962ccd6737d48eecbb6c49;hpb=ad6bf1a1380ac5cf48d58a7b7969fd45b7b6a49d;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git diff --git a/Translator.hs b/Translator.hs index babd622..b4301a3 100644 --- a/Translator.hs +++ b/Translator.hs @@ -10,6 +10,7 @@ import qualified Maybe import qualified Module import qualified Control.Monad.State as State import Name +import qualified Data.Map as Map import Data.Generics import NameEnv ( lookupNameEnv ) import HscTypes ( cm_binds, cm_types ) @@ -53,7 +54,7 @@ main = let binds = Maybe.mapMaybe (findBind (cm_binds core)) ["sfull_adder"] liftIO $ putStr $ prettyShow binds -- Turn bind into VHDL - let (vhdl, sess) = State.runState (mkVHDL binds) (VHDLSession core 0 []) + let (vhdl, sess) = State.runState (mkVHDL binds) (VHDLSession core 0 Map.empty) liftIO $ putStr $ render $ ForSyDe.Backend.Ppr.ppr vhdl liftIO $ ForSyDe.Backend.VHDL.FileIO.writeDesignFile vhdl "../vhdl/vhdl/output.vhdl" liftIO $ putStr $ "\n\nFinal session:\n" ++ prettyShow sess ++ "\n\n" @@ -62,9 +63,9 @@ main = -- Turns the given bind into VHDL mkVHDL binds = do -- Add the builtin functions - --mapM (uncurry addFunc) builtin_funcs + mapM addBuiltIn builtin_funcs -- Create entities and architectures for them - mapM flattenBind binds + mapM processBind binds return $ AST.DesignFile [] [] @@ -79,23 +80,33 @@ findBind binds lookfor = NonRec var _ -> lookfor == (occNameString $ nameOccName $ getName var) ) binds --- | Flattens the given bind and adds it to the session. Then (recursively) --- finds any functions it uses and does the same with them. -flattenBind :: - CoreBind -- The binder to flatten +-- | Processes the given bind as a top level bind. +processBind :: + CoreBind -- The bind to process -> VHDLState () -flattenBind (Rec _) = error "Recursive binders not supported" - -flattenBind bind@(NonRec var expr) = do +processBind (Rec _) = error "Recursive binders not supported" +processBind bind@(NonRec var expr) = do -- Create the function signature let ty = CoreUtils.exprType expr let hsfunc = mkHsFunction var ty - --hwfunc <- mkHWFunction bind hsfunc - -- Add it to the session - --addFunc hsfunc hwfunc + flattenBind hsfunc bind + +-- | Flattens the given bind into the given signature and adds it to the +-- session. Then (recursively) finds any functions it uses and does the same +-- with them. +flattenBind :: + HsFunction -- The signature to flatten into + -> CoreBind -- The bind to flatten + -> VHDLState () + +flattenBind _ (Rec _) = error "Recursive binders not supported" + +flattenBind hsfunc bind@(NonRec var expr) = do + -- Flatten the function let flatfunc = flattenFunction hsfunc bind - addFunc hsfunc flatfunc + addFunc hsfunc + setFlatFunc hsfunc flatfunc let used_hsfuncs = map appFunc (apps flatfunc) State.mapM resolvFunc used_hsfuncs return () @@ -121,7 +132,7 @@ resolvFunc hsfunc = do let bind = findBind (cm_binds core) name case bind of Nothing -> error $ "Couldn't find function " ++ name ++ " in current module." - Just b -> flattenBind b + Just b -> flattenBind hsfunc b where name = hsFuncName hsfunc @@ -168,4 +179,25 @@ splitTupleType ty = Nothing Nothing -> Nothing +-- | A consise representation of a (set of) ports on a builtin function +type PortMap = HsValueMap (String, AST.TypeMark) +-- | A consise representation of a builtin function +data BuiltIn = BuiltIn String [PortMap] PortMap + +-- | Translate a concise representation of a builtin function to something +-- that can be put into FuncMap directly. +addBuiltIn :: BuiltIn -> VHDLState () +addBuiltIn (BuiltIn name args res) = do + addFunc hsfunc + where + hsfunc = HsFunction name (map useAsPort args) (useAsPort res) + +builtin_funcs = + [ + BuiltIn "hwxor" [(Single ("a", VHDL.bit_ty)), (Single ("b", VHDL.bit_ty))] (Single ("o", VHDL.bit_ty)), + BuiltIn "hwand" [(Single ("a", VHDL.bit_ty)), (Single ("b", VHDL.bit_ty))] (Single ("o", VHDL.bit_ty)), + BuiltIn "hwor" [(Single ("a", VHDL.bit_ty)), (Single ("b", VHDL.bit_ty))] (Single ("o", VHDL.bit_ty)), + BuiltIn "hwnot" [(Single ("a", VHDL.bit_ty))] (Single ("o", VHDL.bit_ty)) + ] + -- vim: set ts=8 sw=2 sts=2 expandtab: