X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;ds=sidebyside;f=Translator.hs;h=98380606884c24ba953a07216d1bb788d1747d22;hb=1e30fe04f4c285970ad2d5e23930dd935b4214fa;hp=c16406be3aef2781484251c56a21d3e5fb394f54;hpb=5b7046a2981a1e65483527cab15314dd140e0002;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/Translator.hs b/Translator.hs
index c16406b..9838060 100644
--- a/Translator.hs
+++ b/Translator.hs
@@ -43,9 +43,9 @@ import qualified VHDL
 
 main = do
   -- Load the module
-  core <- loadModule "Adders.hs"
+  core <- loadModule "Alu.hs"
   -- Translate to VHDL
-  vhdl <- moduleToVHDL core ["dff"]
+  vhdl <- moduleToVHDL core ["salu"]
   -- Write VHDL to file
   writeVHDL vhdl "../vhdl/vhdl/output.vhdl"