X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;ds=sidebyside;f=Translator.hs;h=75a875bf8426e43f157e0ab6bf07f3435329326d;hb=e771c40c12c3d93a1c59b396cf862cb0ac617d94;hp=53befc228e6ef947107b72141d9cb7c713fd5606;hpb=c77b7153a516c7dab7824520dd391189270a570b;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/Translator.hs b/Translator.hs
index 53befc2..75a875b 100644
--- a/Translator.hs
+++ b/Translator.hs
@@ -42,10 +42,14 @@ import VHDLTypes
 import qualified VHDL
 
 main = do
+  makeVHDL "Alu.hs" "salu"
+
+makeVHDL :: String -> String -> IO ()
+makeVHDL filename name = do
   -- Load the module
-  core <- loadModule "Adders.hs"
+  core <- loadModule filename
   -- Translate to VHDL
-  vhdl <- moduleToVHDL core ["sfull_adder"]
+  vhdl <- moduleToVHDL core [name]
   -- Write VHDL to file
   writeVHDL vhdl "../vhdl/vhdl/output.vhdl"
 
@@ -56,6 +60,7 @@ listBind filename name = do
   let binds = findBinds core [name]
   putStr "\n"
   putStr $ prettyShow binds
+  putStr $ showSDoc $ ppr binds
   putStr "\n\n"
 
 -- | Translate the binds with the given names from the given core module to