X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;ds=sidebyside;f=Translator.hs;h=6a784251d3c310240fc657b8a0c183980cc80202;hb=d3a445954d4e2f93ff64839f4db72e7541b69a86;hp=5e36b3856b631666cc4fb62fb932631e21a33943;hpb=bf0b6fedf46d525cc7e4d389b4fb7dd539174939;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

diff --git a/Translator.hs b/Translator.hs
index 5e36b38..6a78425 100644
--- a/Translator.hs
+++ b/Translator.hs
@@ -92,7 +92,7 @@ moduleToVHDL core list = do
       -- Create entities and architectures for them
       Monad.zipWithM processBind statefuls binds
       modFuncs nameFlatFunction
-      modFuncs VHDL.createEntity
+      modFuncMap $ Map.mapWithKey (\hsfunc fdata -> fdata {funcEntity = VHDL.createEntity hsfunc fdata})
       modFuncs VHDL.createArchitecture
       funcs <- getFuncs
       return $ VHDL.getDesignFiles (map snd funcs)