X-Git-Url: https://git.stderr.nl/gitweb?a=blobdiff_plain;ds=sidebyside;f=Generate.hs;h=7de216129dfbed6cf4d55fb4e415d00fbc746c19;hb=0c113a538aa9a891935665481782bdce8350e345;hp=de8c1a6604699320024636b3d5e32a5eab7c576d;hpb=a0c01abba26d4c00428d340d068f87a84afbc917;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git diff --git a/Generate.hs b/Generate.hs index de8c1a6..7de2161 100644 --- a/Generate.hs +++ b/Generate.hs @@ -5,6 +5,7 @@ import qualified Control.Monad as Monad import qualified Data.Map as Map import qualified Maybe import Data.Accessor +import Debug.Trace -- ForSyDe import qualified ForSyDe.Backend.VHDL.AST as AST @@ -19,32 +20,67 @@ import Constants import VHDLTypes import VHDLTools import CoreTools +import Pretty + +-- | A function to wrap a builder-like function that expects its arguments to +-- be expressions. +genExprArgs :: + (dst -> func -> [AST.Expr] -> res) + -> (dst -> func -> [CoreSyn.CoreExpr] -> res) +genExprArgs wrap dst func args = wrap dst func args' + where args' = map (varToVHDLExpr.exprToVar) args + +-- | A function to wrap a builder-like function that expects its arguments to +-- be variables. +genVarArgs :: + (dst -> func -> [Var.Var] -> res) + -> (dst -> func -> [CoreSyn.CoreExpr] -> res) +genVarArgs wrap dst func args = wrap dst func args' + where args' = map exprToVar args + +-- | A function to wrap a builder-like function that produces an expression +-- and expects it to be assigned to the destination. +genExprRes :: + (CoreSyn.CoreBndr -> func -> [arg] -> VHDLSession AST.Expr) + -> (CoreSyn.CoreBndr -> func -> [arg] -> VHDLSession [AST.ConcSm]) +genExprRes wrap dst func args = do + expr <- wrap dst func args + return $ [mkUncondAssign (Left dst) expr] -- | Generate a binary operator application. The first argument should be a -- constructor from the AST.Expr type, e.g. AST.And. -genExprOp2 :: (AST.Expr -> AST.Expr -> AST.Expr) -> CoreSyn.CoreBndr -> [AST.Expr] -> VHDLSession AST.Expr -genExprOp2 op res [arg1, arg2] = return $ op arg1 arg2 +genOperator2 :: (AST.Expr -> AST.Expr -> AST.Expr) -> BuiltinBuilder +genOperator2 op = genExprArgs $ genExprRes (genOperator2' op) +genOperator2' :: (AST.Expr -> AST.Expr -> AST.Expr) -> CoreSyn.CoreBndr -> CoreSyn.CoreBndr -> [AST.Expr] -> VHDLSession AST.Expr +genOperator2' op res f [arg1, arg2] = return $ op arg1 arg2 -- | Generate a unary operator application -genExprOp1 :: (AST.Expr -> AST.Expr) -> CoreSyn.CoreBndr -> [AST.Expr] -> VHDLSession AST.Expr -genExprOp1 op res [arg] = return $ op arg +genOperator1 :: (AST.Expr -> AST.Expr) -> BuiltinBuilder +genOperator1 op = genExprArgs $ genExprRes (genOperator1' op) +genOperator1' :: (AST.Expr -> AST.Expr) -> CoreSyn.CoreBndr -> CoreSyn.CoreBndr -> [AST.Expr] -> VHDLSession AST.Expr +genOperator1' op res f [arg] = return $ op arg -- | Generate a function call from the destination binder, function name and a -- list of expressions (its arguments) -genExprFCall :: String -> CoreSyn.CoreBndr -> [AST.Expr] -> VHDLSession AST.Expr -genExprFCall fname res args = do +genFCall :: BuiltinBuilder +genFCall = genExprArgs $ genExprRes genFCall' +genFCall' :: CoreSyn.CoreBndr -> CoreSyn.CoreBndr -> [AST.Expr] -> VHDLSession AST.Expr +genFCall' res f args = do + let fname = varToString f let el_ty = (tfvec_elem . Var.varType) res id <- vectorFunId el_ty fname return $ AST.PrimFCall $ AST.FCall (AST.NSimple id) $ map (\exp -> Nothing AST.:=>: AST.ADExpr exp) args -- | Generate a generate statement for the builtin function "map" -genMapCall :: - Entity -- | The entity to map - -> [CoreSyn.CoreBndr] -- | The vectors - -> VHDLSession AST.GenerateSm -- | The resulting generate statement -genMapCall entity [arg, res] = return $ genSm - where +genMap :: BuiltinBuilder +genMap = genVarArgs genMap' +genMap' res f [mapped_f, arg] = do + signatures <- getA vsSignatures + let entity = Maybe.fromMaybe + (error $ "Using function '" ++ (varToString mapped_f) ++ "' without signature? This should not happen!") + (Map.lookup mapped_f signatures) + let -- Setup the generate scheme len = (tfvec_len . Var.varType) res label = mkVHDLExtId ("mapVector" ++ (varToString res)) @@ -53,10 +89,10 @@ genMapCall entity [arg, res] = return $ genSm genScheme = AST.ForGn nPar range -- Get the entity name and port names entity_id = ent_id entity - argport = map (Monad.liftM fst) (ent_args entity) + argports = map (Monad.liftM fst) (ent_args entity) resport = (Monad.liftM fst) (ent_res entity) -- Assign the ports - inport = mkAssocElemIndexed (head argport) (varToString arg) nPar + inport = mkAssocElemIndexed (argports!!0) (varToString arg) nPar outport = mkAssocElemIndexed resport (varToString res) nPar clk_port = mkAssocElem (Just $ mkVHDLExtId "clk") "clk" portassigns = Maybe.catMaybes [inport,outport,clk_port] @@ -64,7 +100,138 @@ genMapCall entity [arg, res] = return $ genSm mapLabel = "map" ++ (AST.fromVHDLId entity_id) compins = mkComponentInst mapLabel entity_id portassigns -- Return the generate functions - genSm = AST.GenerateSm label genScheme [] [compins] + genSm = AST.CSGSm $ AST.GenerateSm label genScheme [] [compins] + in + return $ [genSm] + +genZipWith :: BuiltinBuilder +genZipWith = genVarArgs genZipWith' +genZipWith' res f args@[zipped_f, arg1, arg2] = do + signatures <- getA vsSignatures + let entity = Maybe.fromMaybe + (error $ "Using function '" ++ (varToString zipped_f) ++ "' without signature? This should not happen!") + (Map.lookup zipped_f signatures) + let + -- Setup the generate scheme + len = (tfvec_len . Var.varType) res + label = mkVHDLExtId ("zipWithVector" ++ (varToString res)) + nPar = AST.unsafeVHDLBasicId "n" + range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1)) + genScheme = AST.ForGn nPar range + -- Get the entity name and port names + entity_id = ent_id entity + argports = map (Monad.liftM fst) (ent_args entity) + resport = (Monad.liftM fst) (ent_res entity) + -- Assign the ports + inport1 = mkAssocElemIndexed (argports!!0) (varToString arg1) nPar + inport2 = mkAssocElemIndexed (argports!!1) (varToString arg2) nPar + outport = mkAssocElemIndexed resport (varToString res) nPar + clk_port = mkAssocElem (Just $ mkVHDLExtId "clk") "clk" + portassigns = Maybe.catMaybes [inport1,inport2,outport,clk_port] + -- Generate the portmap + mapLabel = "zipWith" ++ (AST.fromVHDLId entity_id) + compins = mkComponentInst mapLabel entity_id portassigns + -- Return the generate functions + genSm = AST.CSGSm $ AST.GenerateSm label genScheme [] [compins] + in + return $ [genSm] + +genFoldl :: BuiltinBuilder +genFoldl = genVarArgs genFoldl' +genFoldl' resVal f [folded_f, startVal, inVec] = do + signatures <- getA vsSignatures + let entity = Maybe.fromMaybe + (error $ "Using function '" ++ (varToString folded_f) ++ "' without signature? This should not happen!") + (Map.lookup folded_f signatures) + let (vec, _) = splitAppTy (Var.varType inVec) + let vecty = Type.mkAppTy vec (Var.varType startVal) + vecType <- vhdl_ty vecty + -- Setup the generate scheme + let len = (tfvec_len . Var.varType) inVec + let genlabel = mkVHDLExtId ("foldlVector" ++ (varToString inVec)) + let blockLabel = mkVHDLExtId ("foldlVector" ++ (varToString startVal)) + let nPar = AST.unsafeVHDLBasicId "n" + let range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1)) + let genScheme = AST.ForGn nPar range + -- Make the intermediate vector + let tmpVec = AST.BDISD $ AST.SigDec (mkVHDLExtId "tmp") vecType Nothing + -- Return the generate functions + let genSm = AST.GenerateSm genlabel genScheme [] [ AST.CSGSm (genFirstCell entity [startVal, inVec, resVal]) + , AST.CSGSm (genOtherCell entity [startVal, inVec, resVal]) + , AST.CSGSm (genLastCell entity [startVal, inVec, resVal]) + ] + return [AST.CSBSm $ AST.BlockSm blockLabel [] (AST.PMapAspect []) [tmpVec] [AST.CSGSm genSm]] + where + genFirstCell :: Entity -> [CoreSyn.CoreBndr] -> AST.GenerateSm + genFirstCell entity [startVal, inVec, resVal] = cellGn + where + cellLabel = mkVHDLExtId "firstcell" + cellGenScheme = AST.IfGn ((AST.PrimName $ AST.NSimple nPar) AST.:=: (AST.PrimLit "0")) + nPar = AST.unsafeVHDLBasicId "n" + -- Get the entity name and port names + entity_id = ent_id entity + argports = map (Monad.liftM fst) (ent_args entity) + resport = (Monad.liftM fst) (ent_res entity) + -- Assign the ports + inport1 = mkAssocElem (argports!!0) (varToString startVal) + inport2 = mkAssocElemIndexed (argports!!1) (varToString inVec) nPar + outport = mkAssocElemIndexed resport "tmp" nPar + clk_port = mkAssocElem (Just $ mkVHDLExtId "clk") "clk" + portassigns = Maybe.catMaybes [inport1,inport2,outport,clk_port] + -- Generate the portmap + mapLabel = "cell" ++ (AST.fromVHDLId entity_id) + compins = mkComponentInst mapLabel entity_id portassigns + -- Return the generate functions + cellGn = AST.GenerateSm cellLabel cellGenScheme [] [compins] + genOtherCell :: Entity -> [CoreSyn.CoreBndr] -> AST.GenerateSm + genOtherCell entity [startVal, inVec, resVal] = cellGn + where + len = (tfvec_len . Var.varType) inVec + cellLabel = mkVHDLExtId "othercell" + cellGenScheme = AST.IfGn $ AST.And ((AST.PrimName $ AST.NSimple nPar) AST.:>: (AST.PrimLit "0")) + ((AST.PrimName $ AST.NSimple nPar) AST.:<: (AST.PrimLit $ show (len-1))) + nPar = AST.unsafeVHDLBasicId "n" + -- Get the entity name and port names + entity_id = ent_id entity + argports = map (Monad.liftM fst) (ent_args entity) + resport = (Monad.liftM fst) (ent_res entity) + -- Assign the ports + inport1 = mkAssocElemIndexed (argports!!0) "tmp" (AST.unsafeVHDLBasicId "n-1") + inport2 = mkAssocElemIndexed (argports!!1) (varToString inVec) nPar + outport = mkAssocElemIndexed resport "tmp" nPar + clk_port = mkAssocElem (Just $ mkVHDLExtId "clk") "clk" + portassigns = Maybe.catMaybes [inport1,inport2,outport,clk_port] + -- Generate the portmap + mapLabel = "cell" ++ (AST.fromVHDLId entity_id) + compins = mkComponentInst mapLabel entity_id portassigns + -- Return the generate functions + cellGn = AST.GenerateSm cellLabel cellGenScheme [] [compins] + genLastCell :: Entity -> [CoreSyn.CoreBndr] -> AST.GenerateSm + genLastCell entity [startVal, inVec, resVal] = cellGn + where + len = (tfvec_len . Var.varType) inVec + cellLabel = mkVHDLExtId "lastCell" + cellGenScheme = AST.IfGn ((AST.PrimName $ AST.NSimple nPar) AST.:=: (AST.PrimLit $ show (len-1))) + nPar = AST.unsafeVHDLBasicId "n" + -- Get the entity name and port names + entity_id = ent_id entity + argports = map (Monad.liftM fst) (ent_args entity) + resport = (Monad.liftM fst) (ent_res entity) + -- Assign the ports + inport1 = mkAssocElemIndexed (argports!!0) "tmp" (AST.unsafeVHDLBasicId "n-1") + inport2 = mkAssocElemIndexed (argports!!1) (varToString inVec) nPar + outport = mkAssocElemIndexed resport "tmp" nPar + clk_port = mkAssocElem (Just $ mkVHDLExtId "clk") "clk" + portassigns = Maybe.catMaybes [inport1,inport2,outport,clk_port] + -- Generate the portmap + mapLabel = "cell" ++ (AST.fromVHDLId entity_id) + compins = mkComponentInst mapLabel entity_id portassigns + -- Generate the output assignment + assign = mkUncondAssign (Left resVal) (AST.PrimName (AST.NIndexed (AST.IndexedName + (AST.NSimple (mkVHDLExtId "tmp")) [AST.PrimLit $ show (len-1)]))) + -- Return the generate functions + cellGn = AST.GenerateSm cellLabel cellGenScheme [] [compins,assign] + -- Returns the VHDLId of the vector function with the given name for the given -- element type. Generates -- this function if needed. @@ -102,7 +269,7 @@ genUnconsVectorFuns elemTM vectorTM = , (takeId, AST.SubProgBody takeSpec [AST.SPVD takeVar] [takeExpr, takeRet]) , (dropId, AST.SubProgBody dropSpec [AST.SPVD dropVar] [dropExpr, dropRet]) , (plusgtId, AST.SubProgBody plusgtSpec [AST.SPVD plusgtVar] [plusgtExpr, plusgtRet]) - , (emptyId, AST.SubProgBody emptySpec [AST.SPVD emptyVar] [emptyExpr]) + , (emptyId, AST.SubProgBody emptySpec [AST.SPCD emptyVar] [emptyExpr]) , (singletonId, AST.SubProgBody singletonSpec [AST.SPVD singletonVar] [singletonRet]) , (copyId, AST.SubProgBody copySpec [AST.SPVD copyVar] [copyExpr]) ] @@ -130,7 +297,7 @@ genUnconsVectorFuns elemTM vectorTM = (Just $ AST.ConstraintIndex $ AST.IndexConstraint [AST.ToRange (AST.PrimLit "0") (AST.PrimName (AST.NAttribute $ - AST.AttribName (AST.NSimple vecPar) (mkVHDLExtId lengthId) Nothing) AST.:-: + AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing) AST.:-: (AST.PrimLit "1")) ])) Nothing -- res AST.:= vec(0 to i-1) & a & vec(i+1 to length'vec-1) @@ -139,7 +306,7 @@ genUnconsVectorFuns elemTM vectorTM = AST.PrimName (AST.NSimple aPar) AST.:&: vecSlice (AST.PrimName (AST.NSimple iPar) AST.:+: AST.PrimLit "1") ((AST.PrimName (AST.NAttribute $ - AST.AttribName (AST.NSimple vecPar) (mkVHDLExtId lengthId) Nothing)) + AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing)) AST.:-: AST.PrimLit "1")) replaceRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId) vecSlice init last = AST.PrimName (AST.NSlice @@ -155,7 +322,7 @@ genUnconsVectorFuns elemTM vectorTM = lastExpr = AST.ReturnSm (Just $ (AST.PrimName $ AST.NIndexed (AST.IndexedName (AST.NSimple vecPar) [AST.PrimName (AST.NAttribute $ - AST.AttribName (AST.NSimple vecPar) (mkVHDLExtId lengthId) Nothing) + AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing) AST.:-: AST.PrimLit "1"]))) initSpec = AST.Function (mkVHDLExtId initId) [AST.IfaceVarDec vecPar vectorTM] vectorTM -- variable res : fsvec_x (0 to vec'length-2); @@ -165,14 +332,14 @@ genUnconsVectorFuns elemTM vectorTM = (Just $ AST.ConstraintIndex $ AST.IndexConstraint [AST.ToRange (AST.PrimLit "0") (AST.PrimName (AST.NAttribute $ - AST.AttribName (AST.NSimple vecPar) (mkVHDLExtId lengthId) Nothing) AST.:-: + AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing) AST.:-: (AST.PrimLit "2")) ])) Nothing -- resAST.:= vec(0 to vec'length-2) initExpr = AST.NSimple resId AST.:= (vecSlice (AST.PrimLit "0") (AST.PrimName (AST.NAttribute $ - AST.AttribName (AST.NSimple vecPar) (mkVHDLExtId lengthId) Nothing) + AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing) AST.:-: AST.PrimLit "2")) initRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId) tailSpec = AST.Function (mkVHDLExtId tailId) [AST.IfaceVarDec vecPar vectorTM] vectorTM @@ -183,14 +350,14 @@ genUnconsVectorFuns elemTM vectorTM = (Just $ AST.ConstraintIndex $ AST.IndexConstraint [AST.ToRange (AST.PrimLit "0") (AST.PrimName (AST.NAttribute $ - AST.AttribName (AST.NSimple vecPar) (mkVHDLExtId lengthId) Nothing) AST.:-: + AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing) AST.:-: (AST.PrimLit "2")) ])) Nothing -- res AST.:= vec(1 to vec'length-1) tailExpr = AST.NSimple resId AST.:= (vecSlice (AST.PrimLit "1") (AST.PrimName (AST.NAttribute $ - AST.AttribName (AST.NSimple vecPar) (mkVHDLExtId lengthId) Nothing) + AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing) AST.:-: AST.PrimLit "1")) tailRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId) takeSpec = AST.Function (mkVHDLExtId takeId) [AST.IfaceVarDec nPar naturalTM, @@ -218,14 +385,14 @@ genUnconsVectorFuns elemTM vectorTM = (Just $ AST.ConstraintIndex $ AST.IndexConstraint [AST.ToRange (AST.PrimLit "0") (AST.PrimName (AST.NAttribute $ - AST.AttribName (AST.NSimple vecPar) (mkVHDLExtId lengthId) Nothing) AST.:-: + AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing) AST.:-: (AST.PrimName $ AST.NSimple nPar)AST.:-: (AST.PrimLit "1")) ])) Nothing -- res AST.:= vec(n to vec'length-1) dropExpr = AST.NSimple resId AST.:= (vecSlice (AST.PrimName $ AST.NSimple nPar) (AST.PrimName (AST.NAttribute $ - AST.AttribName (AST.NSimple vecPar) (mkVHDLExtId lengthId) Nothing) + AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing) AST.:-: AST.PrimLit "1")) dropRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId) plusgtSpec = AST.Function (mkVHDLExtId plusgtId) [AST.IfaceVarDec aPar elemTM, @@ -237,7 +404,7 @@ genUnconsVectorFuns elemTM vectorTM = (Just $ AST.ConstraintIndex $ AST.IndexConstraint [AST.ToRange (AST.PrimLit "0") (AST.PrimName (AST.NAttribute $ - AST.AttribName (AST.NSimple vecPar) (mkVHDLExtId lengthId) Nothing))])) + AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing))])) Nothing plusgtExpr = AST.NSimple resId AST.:= ((AST.PrimName $ AST.NSimple aPar) AST.:&: @@ -245,12 +412,9 @@ genUnconsVectorFuns elemTM vectorTM = plusgtRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId) emptySpec = AST.Function (mkVHDLExtId emptyId) [] vectorTM emptyVar = - AST.VarDec resId - (AST.SubtypeIn vectorTM - (Just $ AST.ConstraintIndex $ AST.IndexConstraint - [AST.ToRange (AST.PrimLit "0") - (AST.PrimLit "-1")])) - Nothing + AST.ConstDec resId + (AST.SubtypeIn vectorTM Nothing) + (Just $ AST.PrimLit "\"\"") emptyExpr = AST.ReturnSm (Just $ AST.PrimName (AST.NSimple resId)) singletonSpec = AST.Function (mkVHDLExtId singletonId) [AST.IfaceVarDec aPar elemTM ] vectorTM