Don't generate a state proc for an empty state.

[matthijs/master-project/cλash.git] / cλash / CLasH / VHDL / VHDLTools.hs

diff --git a/cλash/CLasH/VHDL/VHDLTools.hs b/cλash/CLasH/VHDL/VHDLTools.hs
index 36d35e3701c4076273d4e3272c6df8fe7457f0ae..b289501d96092b328e00e36177f720493af69745 100644 (file)
--- a/cλash/CLasH/VHDL/VHDLTools.hs
+++ b/cλash/CLasH/VHDL/VHDLTools.hs
@@ -88,9 +88,9 @@ mkAssocElems ::
   [AST.Expr]                    -- ^ The argument that are applied to function
   -> AST.VHDLName               -- ^ The binder in which to store the result
   -> Entity                     -- ^ The entity to map against.
-  -> TranslatorSession [AST.AssocElem] -- ^ The resulting port maps
+  -> [AST.AssocElem]            -- ^ The resulting port maps
 mkAssocElems args res entity =
-    return $ arg_maps ++ (Maybe.maybeToList res_map_maybe)
+    arg_maps ++ (Maybe.maybeToList res_map_maybe)
   where
     arg_ports = ent_args entity
     res_port_maybe = ent_res entity