import qualified Control.Monad as Monad
import qualified Maybe
import qualified Data.Map as Map
-import Data.Accessor
-import qualified Data.Accessor.MonadState as MonadState
+import qualified Data.Accessor.Monad.Trans.State as MonadState
--- ForSyDe
+-- VHDL Imports
import qualified Language.VHDL.AST as AST
-- GHC API
-import CoreSyn
+import qualified CoreSyn
import qualified HscTypes
import qualified Var
import qualified TysWiredIn
-> [HscTypes.CoreModule] -- ^ Compiled modules
-> CoreSyn.CoreExpr -- ^ Input stimuli
-> CoreSyn.CoreBndr -- ^ Top Entity
- -> TranslatorSession CoreBndr -- ^ The id of the generated archictecture
+ -> TranslatorSession CoreSyn.CoreBndr -- ^ The id of the generated archictecture
createTestbench mCycles cores stimuli top = do
stimuli' <- reduceCoreListToHsList cores stimuli
-- Create a binder for the testbench. We use the unit type (), since the
-- testbench has no outputs and no inputs.
bndr <- mkInternalVar "testbench" TysWiredIn.unitTy
let entity = createTestbenchEntity bndr
- modA tsEntities (Map.insert bndr entity)
+ MonadState.modify tsEntities (Map.insert bndr entity)
arch <- createTestbenchArch mCycles stimuli' top entity
- modA tsArchitectures (Map.insert bndr arch)
+ MonadState.modify tsArchitectures (Map.insert bndr arch)
return bndr
createTestbenchEntity ::
let ([], binds, res) = splitNormalized expr
(stimulansbindss, useds) <- unzipM $ Monad.mapM mkConcSm binds
sig_dec_maybes <- mapM (mkSigDec . fst) (filter ((/=res).fst) binds)
- let sig_decs = map (AST.BDISD) (Maybe.catMaybes $ sig_dec_maybes)
+ let sig_decs = map (AST.BDISD) (Maybe.catMaybes sig_dec_maybes)
let block_label = mkVHDLExtId ("testcycle_" ++ (show cycl))
let block = AST.BlockSm block_label [] (AST.PMapAspect []) sig_decs (concat stimulansbindss)
case (sig_decs,(concat stimulansbindss)) of
[clockId]
[AST.IfSm clkPred (writeOuts outs) [] Nothing]
where clkPred = AST.PrimName (AST.NAttribute $ AST.AttribName (AST.NSimple clockId)
- (AST.NSimple $ eventId)
+ (AST.NSimple eventId)
Nothing ) `AST.And`
(AST.PrimName (AST.NSimple clockId) AST.:=: AST.PrimLit "'1'")
writeOuts :: [AST.VHDLId] -> [AST.SeqSm]