---
-- Functions to create a VHDL testbench from a list of test input.
--
module CLasH.VHDL.Testbench where
bndr <- mkInternalVar "testbench" TysWiredIn.unitTy
let entity = createTestbenchEntity bndr
modA tsEntities (Map.insert bndr entity)
- arch <- createTestbenchArch mCycles stimuli' top
+ arch <- createTestbenchArch mCycles stimuli' top entity
modA tsArchitectures (Map.insert bndr arch)
return bndr
Maybe Int -- ^ Number of cycles to simulate
-> [CoreSyn.CoreExpr] -- ^ Imput stimuli
-> CoreSyn.CoreBndr -- ^ Top Entity
+ -> Entity -- ^ The signature to create an architecture for
-> TranslatorSession (Architecture, [CoreSyn.CoreBndr])
-- ^ The architecture and any other entities used.
-createTestbenchArch mCycles stimuli top = do
+createTestbenchArch mCycles stimuli top testent= do
signature <- getEntity top
let entId = ent_id signature
iIface = ent_args signature
[AST.SigDec clockId std_logicTM (Just $ AST.PrimLit "'0'"),
AST.SigDec resetId std_logicTM (Just $ AST.PrimLit "'0'")]
let oDecs = AST.SigDec (fst oIface) (snd oIface) Nothing
- let portmaps = mkAssocElems (map idToVHDLExpr iIds) (AST.NSimple oId) signature
+ portmaps <- mkAssocElems (map idToVHDLExpr iIds) (AST.NSimple oId) signature
let mIns = mkComponentInst "totest" entId portmaps
(stimuliAssigns, stimuliDecs, cycles, used) <- createStimuliAssigns mCycles stimuli (head iIds)
let finalAssigns = (AST.CSSASm (AST.NSimple resetId AST.:<==:
let outputProc = createOutputProc [oId]
let arch = AST.ArchBody
(AST.unsafeVHDLBasicId "test")
- (AST.NSimple $ AST.unsafeIdAppend entId "_tb")
+ (AST.NSimple $ ent_id testent)
(map AST.BDISD (finalIDecs ++ stimuliDecs ++ [oDecs]))
(mIns :
( (AST.CSPSm clkProc) : (AST.CSPSm outputProc) : finalAssigns ) )