-- GHC API
import CoreSyn
+import qualified HscTypes
import qualified Var
import qualified TysWiredIn
createTestbench ::
Maybe Int -- ^ Number of cycles to simulate
+ -> [HscTypes.CoreModule] -- ^ Compiled modules
-> CoreSyn.CoreExpr -- ^ Input stimuli
-> CoreSyn.CoreBndr -- ^ Top Entity
-> TranslatorSession CoreBndr -- ^ The id of the generated archictecture
-createTestbench mCycles stimuli top = do
- let stimuli' = reduceCoreListToHsList stimuli
+createTestbench mCycles cores stimuli top = do
+ stimuli' <- reduceCoreListToHsList cores stimuli
-- Create a binder for the testbench. We use the unit type (), since the
-- testbench has no outputs and no inputs.
bndr <- mkInternalVar "testbench" TysWiredIn.unitTy
Maybe Int -- ^ Number of cycles to simulate
-> [CoreSyn.CoreExpr] -- ^ Input stimuli
-> AST.VHDLId -- ^ Input signal
- -> TranslatorSession ( [AST.ConcSm] -- ^ Resulting statemetns
- , [AST.SigDec] -- ^ Needed signals
- , Int -- ^ The number of cycles to simulate
- , [CoreSyn.CoreBndr]) -- ^ Any entities used
+ -> TranslatorSession ( [AST.ConcSm]
+ , [AST.SigDec]
+ , Int
+ , [CoreSyn.CoreBndr]) -- ^ (Resulting statements, Needed signals, The number of cycles to simulate, Any entities used)
createStimuliAssigns mCycles [] _ = return ([], [], Maybe.maybe 0 id mCycles, [])
createStimuliAssigns mCycles stimuli signal = do
createStimulans ::
CoreSyn.CoreExpr -- ^ The stimulans
-> Int -- ^ The cycle for this stimulans
- -> TranslatorSession ( AST.ConcSm -- ^ The statement
- , Var.Var -- ^ the variable it assigns to (assumed to be available!)
- , [CoreSyn.CoreBndr]) -- ^ Any entities used by this stimulans
+ -> TranslatorSession ( AST.ConcSm
+ , Var.Var
+ , [CoreSyn.CoreBndr]) -- ^ (The statement, the variable it assigns to (assumed to be available!), Any entities used by this stimulans)
createStimulans expr cycl = do
-- There must be a let at top level