Fix comment.

[matthijs/master-project/cλash.git] / cλash / CLasH / VHDL / Testbench.hs

diff --git a/cλash/CLasH/VHDL/Testbench.hs b/cλash/CLasH/VHDL/Testbench.hs
index 76fc0739f5d21537575c76d0d3a703d5beae76a3..235dda60c863b38f1a8616cbe71390c7bd07da50 100644 (file)
--- a/cλash/CLasH/VHDL/Testbench.hs
+++ b/cλash/CLasH/VHDL/Testbench.hs
@@ -1,4 +1,3 @@
--- 
 -- Functions to create a VHDL testbench from a list of test input.
 --
 module CLasH.VHDL.Testbench where
@@ -15,6 +14,7 @@ import qualified Language.VHDL.AST as AST
 
 -- GHC API
 import CoreSyn
+import qualified HscTypes
 import qualified Var
 import qualified TysWiredIn
 
@@ -31,11 +31,12 @@ import CLasH.Utils
 
 createTestbench :: 
   Maybe Int -- ^ Number of cycles to simulate
+  -> [HscTypes.CoreModule] -- ^ Compiled modules
   -> CoreSyn.CoreExpr -- ^ Input stimuli
   -> CoreSyn.CoreBndr -- ^ Top Entity
   -> TranslatorSession CoreBndr -- ^ The id of the generated archictecture
-createTestbench mCycles stimuli top = do
-  let stimuli' = reduceCoreListToHsList stimuli
+createTestbench mCycles cores stimuli top = do
+  stimuli' <- reduceCoreListToHsList cores stimuli
   -- Create a binder for the testbench. We use the unit type (), since the
   -- testbench has no outputs and no inputs.
   bndr <- mkInternalVar "testbench" TysWiredIn.unitTy
@@ -75,7 +76,7 @@ createTestbenchArch mCycles stimuli top testent= do
                     [AST.SigDec clockId std_logicTM (Just $ AST.PrimLit "'0'"),
                      AST.SigDec resetId std_logicTM (Just $ AST.PrimLit "'0'")]
   let oDecs   = AST.SigDec (fst oIface) (snd oIface) Nothing
-  let portmaps = mkAssocElems (map idToVHDLExpr iIds) (AST.NSimple oId) signature
+  portmaps <- mkAssocElems (map idToVHDLExpr iIds) (AST.NSimple oId) signature
   let mIns    = mkComponentInst "totest" entId portmaps
   (stimuliAssigns, stimuliDecs, cycles, used) <- createStimuliAssigns mCycles stimuli (head iIds)
   let finalAssigns = (AST.CSSASm (AST.NSimple resetId AST.:<==:
@@ -96,10 +97,10 @@ createStimuliAssigns ::
   Maybe Int -- ^ Number of cycles to simulate
   -> [CoreSyn.CoreExpr] -- ^ Input stimuli
   -> AST.VHDLId -- ^ Input signal
-  -> TranslatorSession ( [AST.ConcSm] -- ^ Resulting statemetns
-                       , [AST.SigDec] -- ^ Needed signals
-                       , Int -- ^ The number of cycles to simulate
-                       , [CoreSyn.CoreBndr]) -- ^ Any entities used
+  -> TranslatorSession ( [AST.ConcSm]
+                       , [AST.SigDec]
+                       , Int
+                       , [CoreSyn.CoreBndr]) -- ^ (Resulting statements, Needed signals, The number of cycles to simulate, Any entities used)
 createStimuliAssigns mCycles [] _ = return ([], [], Maybe.maybe 0 id mCycles, [])
 
 createStimuliAssigns mCycles stimuli signal = do
@@ -117,9 +118,9 @@ createStimuliAssigns mCycles stimuli signal = do
 createStimulans ::
   CoreSyn.CoreExpr -- ^ The stimulans
   -> Int -- ^ The cycle for this stimulans
-  -> TranslatorSession ( AST.ConcSm -- ^ The statement
-                       , Var.Var -- ^ the variable it assigns to (assumed to be available!)
-                       , [CoreSyn.CoreBndr]) -- ^ Any entities used by this stimulans
+  -> TranslatorSession ( AST.ConcSm
+                       , Var.Var 
+                       , [CoreSyn.CoreBndr]) -- ^ (The statement, the variable it assigns to (assumed to be available!), Any entities used by this stimulans)
 
 createStimulans expr cycl = do 
   -- There must be a let at top level