---
-- Functions to create a VHDL testbench from a list of test input.
--
module CLasH.VHDL.Testbench where
-- GHC API
import CoreSyn
+import qualified HscTypes
import qualified Var
import qualified TysWiredIn
createTestbench ::
Maybe Int -- ^ Number of cycles to simulate
+ -> [HscTypes.CoreModule] -- ^ Compiled modules
-> CoreSyn.CoreExpr -- ^ Input stimuli
-> CoreSyn.CoreBndr -- ^ Top Entity
-> TranslatorSession CoreBndr -- ^ The id of the generated archictecture
-createTestbench mCycles stimuli top = do
- let stimuli' = reduceCoreListToHsList stimuli
+createTestbench mCycles cores stimuli top = do
+ stimuli' <- reduceCoreListToHsList cores stimuli
-- Create a binder for the testbench. We use the unit type (), since the
-- testbench has no outputs and no inputs.
bndr <- mkInternalVar "testbench" TysWiredIn.unitTy
let entity = createTestbenchEntity bndr
modA tsEntities (Map.insert bndr entity)
- arch <- createTestbenchArch mCycles stimuli' top
+ arch <- createTestbenchArch mCycles stimuli' top entity
modA tsArchitectures (Map.insert bndr arch)
return bndr
Maybe Int -- ^ Number of cycles to simulate
-> [CoreSyn.CoreExpr] -- ^ Imput stimuli
-> CoreSyn.CoreBndr -- ^ Top Entity
+ -> Entity -- ^ The signature to create an architecture for
-> TranslatorSession (Architecture, [CoreSyn.CoreBndr])
-- ^ The architecture and any other entities used.
-createTestbenchArch mCycles stimuli top = do
+createTestbenchArch mCycles stimuli top testent= do
signature <- getEntity top
let entId = ent_id signature
iIface = ent_args signature
[AST.SigDec clockId std_logicTM (Just $ AST.PrimLit "'0'"),
AST.SigDec resetId std_logicTM (Just $ AST.PrimLit "'0'")]
let oDecs = AST.SigDec (fst oIface) (snd oIface) Nothing
- let portmaps = mkAssocElems (map idToVHDLExpr iIds) (AST.NSimple oId) signature
+ portmaps <- mkAssocElems (map idToVHDLExpr iIds) (AST.NSimple oId) signature
let mIns = mkComponentInst "totest" entId portmaps
(stimuliAssigns, stimuliDecs, cycles, used) <- createStimuliAssigns mCycles stimuli (head iIds)
let finalAssigns = (AST.CSSASm (AST.NSimple resetId AST.:<==:
let outputProc = createOutputProc [oId]
let arch = AST.ArchBody
(AST.unsafeVHDLBasicId "test")
- (AST.NSimple $ AST.unsafeIdAppend entId "_tb")
+ (AST.NSimple $ ent_id testent)
(map AST.BDISD (finalIDecs ++ stimuliDecs ++ [oDecs]))
(mIns :
( (AST.CSPSm clkProc) : (AST.CSPSm outputProc) : finalAssigns ) )
Maybe Int -- ^ Number of cycles to simulate
-> [CoreSyn.CoreExpr] -- ^ Input stimuli
-> AST.VHDLId -- ^ Input signal
- -> TranslatorSession ( [AST.ConcSm] -- ^ Resulting statemetns
- , [AST.SigDec] -- ^ Needed signals
- , Int -- ^ The number of cycles to simulate
- , [CoreSyn.CoreBndr]) -- ^ Any entities used
+ -> TranslatorSession ( [AST.ConcSm]
+ , [AST.SigDec]
+ , Int
+ , [CoreSyn.CoreBndr]) -- ^ (Resulting statements, Needed signals, The number of cycles to simulate, Any entities used)
createStimuliAssigns mCycles [] _ = return ([], [], Maybe.maybe 0 id mCycles, [])
createStimuliAssigns mCycles stimuli signal = do
createStimulans ::
CoreSyn.CoreExpr -- ^ The stimulans
-> Int -- ^ The cycle for this stimulans
- -> TranslatorSession ( AST.ConcSm -- ^ The statement
- , Var.Var -- ^ the variable it assigns to (assumed to be available!)
- , [CoreSyn.CoreBndr]) -- ^ Any entities used by this stimulans
+ -> TranslatorSession ( AST.ConcSm
+ , Var.Var
+ , [CoreSyn.CoreBndr]) -- ^ (The statement, the variable it assigns to (assumed to be available!), Any entities used by this stimulans)
createStimulans expr cycl = do
-- There must be a let at top level