Merge branch 'master' of http://git.stderr.nl/matthijs/master-project/cλash

[matthijs/master-project/cλash.git] / cλash / CLasH / VHDL / Constants.hs

diff --git a/cλash/CLasH/VHDL/Constants.hs b/cλash/CLasH/VHDL/Constants.hs
index 71c1c2135b7b1b1d092505279bf91388577d2b5a..e6381fd7411037d5d6051143db3a44b6552d956f 100644 (file)
--- a/cλash/CLasH/VHDL/Constants.hs
+++ b/cλash/CLasH/VHDL/Constants.hs
@@ -1,7 +1,22 @@
 module CLasH.VHDL.Constants where
-  
+
+-- VHDL Imports  
 import qualified Language.VHDL.AST as AST
 
+-- | A list of all builtin functions. Partly duplicates the name table
+-- in VHDL.Generate, but we can't use that map everywhere due to
+-- circular dependencie.
+builtinIds = [ exId, replaceId, headId, lastId, tailId, initId, takeId, dropId
+             , selId, plusgtId, ltplusId, plusplusId, mapId, zipWithId, foldlId
+             , foldrId, zipId, unzipId, shiftlId, shiftrId, rotlId, rotrId
+             , concatId, reverseId, iteratenId, iterateId, generatenId, generateId
+             , emptyId, singletonId, copynId, copyId, lengthTId, nullId
+             , hwxorId, hwandId, hworId, hwnotId, equalityId, inEqualityId, ltId
+             , lteqId, gtId, gteqId, boolOrId, boolAndId, plusId, timesId
+             , negateId, minusId, fromSizedWordId, fromIntegerId, resizeWordId
+             , resizeIntId, sizedIntId, smallIntegerId, fstId, sndId, blockRAMId
+             , splitId, minimumId 
+             ]
 --------------
 -- Identifiers
 --------------
@@ -235,6 +250,9 @@ fstId = "fst"
 sndId :: String
 sndId = "snd"
 
+splitId :: String
+splitId = "split"
+
 -- Equality Operations
 equalityId :: String
 equalityId = "=="
@@ -242,12 +260,27 @@ equalityId = "=="
 inEqualityId :: String
 inEqualityId = "/="
 
+gtId :: String
+gtId = ">"
+
+ltId :: String
+ltId = "<"
+
+gteqId :: String
+gteqId = ">="
+
+lteqId :: String
+lteqId = "<="
+
 boolOrId :: String
 boolOrId = "||"
 
 boolAndId :: String
 boolAndId = "&&"
 
+boolNot :: String
+boolNot = "not"
+
 -- Numeric Operations
 
 -- | plus operation identifier
@@ -285,6 +318,12 @@ toUnsignedId = "to_unsigned"
 resizeId :: String
 resizeId = "resize"
 
+resizeWordId :: String
+resizeWordId = "resizeWord"
+
+resizeIntId :: String
+resizeIntId = "resizeInt"
+
 smallIntegerId :: String
 smallIntegerId = "smallInteger"
 
@@ -354,4 +393,4 @@ stringTM = AST.unsafeVHDLBasicId "string"
 
 -- | tup VHDLName suffix
 tupVHDLSuffix :: AST.VHDLId -> AST.Suffix
-tupVHDLSuffix id = AST.SSimple id
\ No newline at end of file
+tupVHDLSuffix id = AST.SSimple id