Add support for translating designs defined over multiple modules

[matthijs/master-project/cλash.git] / cλash / CLasH / Translator.hs

diff --git a/cλash/CLasH/Translator.hs b/cλash/CLasH/Translator.hs
index c4daf04d0dedb9963e79b1d860b24644321c5d05..f60d225f8bed1ac4f80804bf0dfc5b66178ffa35 100644 (file)
--- a/cλash/CLasH/Translator.hs
+++ b/cλash/CLasH/Translator.hs
@@ -42,10 +42,9 @@ makeVHDLStrings ::
   -> String     -- ^ The TopEntity
   -> String     -- ^ The InitState
   -> String     -- ^ The TestInput
-  -> Bool       -- ^ Is it stateful? (in case InitState is empty)
   -> IO ()
-makeVHDLStrings libdir filenames topentity initstate testinput stateful = do
-  makeVHDL libdir filenames finder stateful
+makeVHDLStrings libdir filenames topentity initstate testinput = do
+  makeVHDL libdir filenames finder
     where
       finder = findSpec (hasVarName topentity)
                         (hasVarName initstate)
@@ -56,10 +55,9 @@ makeVHDLStrings libdir filenames topentity initstate testinput stateful = do
 makeVHDLAnnotations :: 
   FilePath      -- ^ The GHC Library Dir
   -> [FilePath] -- ^ The FileNames
-  -> Bool       -- ^ Is it stateful? (in case InitState is not specified)
   -> IO ()
-makeVHDLAnnotations libdir filenames stateful = do
-  makeVHDL libdir filenames finder stateful
+makeVHDLAnnotations libdir filenames = do
+  makeVHDL libdir filenames finder
     where
       finder = findSpec (hasCLasHAnnotation isTopEntity)
                         (hasCLasHAnnotation isInitState)
@@ -71,45 +69,44 @@ makeVHDL ::
   FilePath      -- ^ The GHC Library Dir
   -> [FilePath] -- ^ The Filenames
   -> Finder
-  -> Bool       -- ^ Indicates if it is meant to be stateful
   -> IO ()
-makeVHDL libdir filenames finder stateful = do
+makeVHDL libdir filenames finder = do
   -- Load the modules
   (cores, env, specs) <- loadModules libdir filenames (Just finder)
   -- Translate to VHDL
-  vhdl <- moduleToVHDL env cores specs stateful
+  vhdl <- moduleToVHDL env cores specs
   -- Write VHDL to file. Just use the first entity for the name
-  let top_entity = (\(t, _, _) -> t) $ head specs
+  let top_entity = head $ Maybe.catMaybes $ map (\(t, _, _) -> t) specs
   let dir = "./vhdl/" ++ (show top_entity) ++ "/"
   prepareDir dir
   mapM (writeVHDL dir) vhdl
   return ()
 
--- | Translate the binds with the given names from the given core module to
---   VHDL. The Bool in the tuple makes the function stateful (True) or
---   stateless (False).
+-- | Translate the specified entities in the given modules to VHDL.
 moduleToVHDL ::
   HscTypes.HscEnv             -- ^ The GHC Environment
   -> [HscTypes.CoreModule]    -- ^ The Core Modules
   -> [EntitySpec]             -- ^ The entities to generate
-  -> Bool                     -- ^ Is it stateful (in case InitState is not specified)
   -> IO [(AST.VHDLId, AST.DesignFile)]
-moduleToVHDL env cores specs stateful = do
+moduleToVHDL env cores specs = do
   vhdl <- runTranslatorSession env $ do
     let all_bindings = concat (map (\x -> CoreSyn.flattenBinds (HscTypes.cm_binds x)) cores)
     -- Store the bindings we loaded
     tsBindings %= Map.fromList all_bindings 
     test_binds <- catMaybesM $ Monad.mapM mkTest specs
-    let topbinds = map (\(top, _, _) -> top) specs
-    createDesignFiles (topbinds ++ test_binds)
+    let topbinds = Maybe.catMaybes $ map (\(top, _, _) -> top) specs
+    case topbinds of
+      []  -> error $ "Could not find top entity requested"
+      tops -> createDesignFiles (tops ++ test_binds)
   mapM (putStr . render . Ppr.ppr . snd) vhdl
   return vhdl
   where
     mkTest :: EntitySpec -> TranslatorSession (Maybe CoreSyn.CoreBndr)
     -- Create a testbench for any entry that has test input
     mkTest (_, _, Nothing) = return Nothing
-    mkTest (top, _, Just input) = do
-      bndr <- createTestbench Nothing input top
+    mkTest (Nothing, _, _) = return Nothing
+    mkTest (Just top, _, Just input) = do
+      bndr <- createTestbench Nothing cores input top
       return $ Just bndr
 
 -- Run the given translator session. Generates a new UniqSupply for that