-- | A specification of an entity we can generate VHDL for. Consists of the
-- binder of the top level entity, an optional initial state and an optional
-- test input.
-type EntitySpec = (CoreSyn.CoreBndr, Maybe CoreSyn.CoreExpr, Maybe CoreSyn.CoreExpr)
+type EntitySpec = (Maybe CoreSyn.CoreBndr, Maybe CoreSyn.CoreExpr, Maybe CoreSyn.CoreExpr)
-- | A function that knows which parts of a module to compile
type Finder =
-----------------------------------------------------------------------------
-- A orderable equivalent of CoreSyn's Type for use as a map key
-newtype OrdType = OrdType { getType :: Type.Type }
+newtype OrdType = OrdType Type.Type
instance Eq OrdType where
(OrdType a) == (OrdType b) = Type.tcEqType a b
instance Ord OrdType where
data HType = StdType OrdType |
ADTType String [HType] |
+ EnumType String [String] |
VecType Int HType |
SizedWType Int |
RangedWType Int |
BuiltinType String
deriving (Eq, Ord)
--- A map of a Core type to the corresponding type name
-type TypeMap = Map.Map HType (AST.VHDLId, Either AST.TypeDef AST.SubtypeIn)
+-- A map of a Core type to the corresponding type name, or Nothing when the
+-- type would be empty.
+type TypeMap = Map.Map HType (Maybe (AST.VHDLId, Either AST.TypeDef AST.SubtypeIn))
-- A map of a vector Core element type and function name to the coressponding
-- VHDLId of the function and the function body.
, tsType_ :: TypeState
, tsBindings_ :: Map.Map CoreSyn.CoreBndr CoreSyn.CoreExpr
, tsNormalized_ :: Map.Map CoreSyn.CoreBndr CoreSyn.CoreExpr
+ , tsEntityCounter_ :: Integer
, tsEntities_ :: Map.Map CoreSyn.CoreBndr Entity
, tsArchitectures_ :: Map.Map CoreSyn.CoreBndr (Architecture, [CoreSyn.CoreBndr])
}