Fixed VHDL Type generation, vhdlTy now uses HType's to generate VHDL Types. Logic...

[matthijs/master-project/cλash.git] / cλash / CLasH / Translator / TranslatorTypes.hs

diff --git a/cλash/CLasH/Translator/TranslatorTypes.hs b/cλash/CLasH/Translator/TranslatorTypes.hs
index 6871861f839c52b8e8e13a18c658689ce215c51c..2591e666f0b3491b93b8f8baaced8d993b77998d 100644 (file)
--- a/cλash/CLasH/Translator/TranslatorTypes.hs
+++ b/cλash/CLasH/Translator/TranslatorTypes.hs
@@ -12,6 +12,7 @@ import qualified Data.Accessor.Template
 import Data.Accessor
 
 -- GHC API
+import qualified GHC
 import qualified CoreSyn
 import qualified Type
 import qualified HscTypes
@@ -22,29 +23,48 @@ import qualified Language.VHDL.AST as AST
 
 -- Local imports
 import CLasH.VHDL.VHDLTypes
+import CLasH.Translator.Annotations
+
+-- | A specification of an entity we can generate VHDL for. Consists of the
+--   binder of the top level entity, an optional initial state and an optional
+--   test input.
+type EntitySpec = (Maybe CoreSyn.CoreBndr, Maybe [(CoreSyn.CoreBndr, CoreSyn.CoreBndr)], Maybe CoreSyn.CoreExpr)
+
+-- | A function that knows which parts of a module to compile
+type Finder =
+  HscTypes.CoreModule -- ^ The module to look at
+  -> GHC.Ghc [EntitySpec]
+
+-----------------------------------------------------------------------------
+-- The TranslatorSession
+-----------------------------------------------------------------------------
 
 -- A orderable equivalent of CoreSyn's Type for use as a map key
-newtype OrdType = OrdType { getType :: Type.Type }
+newtype OrdType = OrdType Type.Type
 instance Eq OrdType where
   (OrdType a) == (OrdType b) = Type.tcEqType a b
 instance Ord OrdType where
   compare (OrdType a) (OrdType b) = Type.tcCmpType a b
 
-data HType = StdType OrdType |
-             ADTType String [HType] |
+data HType = AggrType String [HType] |
+             EnumType String [String] |
              VecType Int HType |
+             UVecType HType |
              SizedWType Int |
              RangedWType Int |
              SizedIType Int |
-             BuiltinType String
-  deriving (Eq, Ord)
+             BuiltinType String |
+             StateType
+  deriving (Eq, Ord, Show)
 
--- A map of a Core type to the corresponding type name
-type TypeMap = Map.Map HType (AST.VHDLId, Either AST.TypeDef AST.SubtypeIn)
+-- A map of a Core type to the corresponding type name, or Nothing when the
+-- type would be empty.
+type TypeMapRec   = Maybe (AST.VHDLId, Maybe (Either AST.TypeDef AST.SubtypeIn))
+type TypeMap      = Map.Map HType TypeMapRec
 
 -- A map of a vector Core element type and function name to the coressponding
 -- VHDLId of the function and the function body.
-type TypeFunMap = Map.Map (OrdType, String) (AST.VHDLId, AST.SubProgBody)
+type TypeFunMap = Map.Map (HType, String) (AST.VHDLId, AST.SubProgBody)
 
 type TfpIntMap = Map.Map OrdType Int
 -- A substate that deals with type generation
@@ -52,7 +72,7 @@ data TypeState = TypeState {
   -- | A map of Core type -> VHDL Type
   tsTypes_      :: TypeMap,
   -- | A list of type declarations
-  tsTypeDecls_  :: [AST.PackageDecItem],
+  tsTypeDecls_  :: [Maybe AST.PackageDecItem],
   -- | A map of vector Core type -> VHDL type function
   tsTypeFuns_   :: TypeFunMap,
   tsTfpInts_    :: TfpIntMap,
@@ -70,8 +90,10 @@ data TranslatorState = TranslatorState {
   , tsType_ :: TypeState
   , tsBindings_ :: Map.Map CoreSyn.CoreBndr CoreSyn.CoreExpr
   , tsNormalized_ :: Map.Map CoreSyn.CoreBndr CoreSyn.CoreExpr
+  , tsEntityCounter_ :: Integer
   , tsEntities_ :: Map.Map CoreSyn.CoreBndr Entity
   , tsArchitectures_ :: Map.Map CoreSyn.CoreBndr (Architecture, [CoreSyn.CoreBndr])
+  , tsInitStates_ :: Map.Map CoreSyn.CoreBndr CoreSyn.CoreBndr
 }
 
 -- Derive accessors
@@ -79,6 +101,10 @@ $( Data.Accessor.Template.deriveAccessors ''TranslatorState )
 
 type TranslatorSession = State.State TranslatorState
 
+-----------------------------------------------------------------------------
+-- Some accessors
+-----------------------------------------------------------------------------
+
 -- Does the given binder reference a top level binder in the current
 -- module(s)?
 isTopLevelBinder :: CoreSyn.CoreBndr -> TranslatorSession Bool
@@ -86,4 +112,20 @@ isTopLevelBinder bndr = do
   bindings <- getA tsBindings
   return $ Map.member bndr bindings
 
+-- Finds the value of a global binding, if available
+getGlobalBind :: CoreSyn.CoreBndr -> TranslatorSession (Maybe CoreSyn.CoreExpr)
+getGlobalBind bndr = do
+  bindings <- getA tsBindings
+  return $ Map.lookup bndr bindings 
+
+-- Adds a new global binding with the given value
+addGlobalBind :: CoreSyn.CoreBndr -> CoreSyn.CoreExpr -> TranslatorSession ()
+addGlobalBind bndr expr = modA tsBindings (Map.insert bndr expr)
+
+-- Returns a list of all global binders
+getGlobalBinders :: TranslatorSession [CoreSyn.CoreBndr]
+getGlobalBinders = do
+  bindings <- getA tsBindings
+  return $ Map.keys bindings
+
 -- vim: set ts=8 sw=2 sts=2 expandtab: