-- Local imports
import CLasH.VHDL.VHDLTypes
+import CLasH.Translator.Annotations
-- | A specification of an entity we can generate VHDL for. Consists of the
-- binder of the top level entity, an optional initial state and an optional
-- test input.
-type EntitySpec = (Maybe CoreSyn.CoreBndr, Maybe CoreSyn.CoreExpr, Maybe CoreSyn.CoreExpr)
+type EntitySpec = (Maybe CoreSyn.CoreBndr, Maybe [(CoreSyn.CoreBndr, CoreSyn.CoreBndr)], Maybe CoreSyn.CoreExpr)
-- | A function that knows which parts of a module to compile
type Finder =
data HType = StdType OrdType |
ADTType String [HType] |
+ EnumType String [String] |
VecType Int HType |
SizedWType Int |
RangedWType Int |
-- A map of a vector Core element type and function name to the coressponding
-- VHDLId of the function and the function body.
-type TypeFunMap = Map.Map (OrdType, String) (AST.VHDLId, AST.SubProgBody)
+type TypeFunMap = Map.Map (HType, String) (AST.VHDLId, AST.SubProgBody)
type TfpIntMap = Map.Map OrdType Int
-- A substate that deals with type generation
, tsEntityCounter_ :: Integer
, tsEntities_ :: Map.Map CoreSyn.CoreBndr Entity
, tsArchitectures_ :: Map.Map CoreSyn.CoreBndr (Architecture, [CoreSyn.CoreBndr])
+ , tsInitStates_ :: Map.Map CoreSyn.CoreBndr CoreSyn.CoreBndr
}
-- Derive accessors