Add predicates for testing representability of types.

[matthijs/master-project/cλash.git] / VHDLTypes.hs

diff --git a/VHDLTypes.hs b/VHDLTypes.hs
index 79d7675f68a48f3663782d0d6c6465d90c0ef871..ff159fa895a6f4c51318eaaf636c2d390e36e2f6 100644 (file)
--- a/VHDLTypes.hs
+++ b/VHDLTypes.hs
@@ -18,21 +18,17 @@ import qualified CoreSyn
 import qualified ForSyDe.Backend.VHDL.AST as AST
 
 -- Local imports
-import FlattenTypes
-import HsValueMap
 
-type VHDLSignalMapElement = (Maybe (AST.VHDLId, AST.TypeMark))
--- | A mapping from a haskell structure to the corresponding VHDL port
---   signature, or Nothing for values that do not translate to a port.
-type VHDLSignalMap = HsValueMap VHDLSignalMapElement
+-- A description of a port of an entity
+type Port = (AST.VHDLId, AST.TypeMark)
 
 -- A description of a VHDL entity. Contains both the entity itself as well as
 -- info on how to map a haskell value (argument / result) on to the entity's
 -- ports.
 data Entity = Entity { 
   ent_id     :: AST.VHDLId,           -- The id of the entity
-  ent_args   :: [VHDLSignalMapElement],      -- A mapping of each function argument to port names
-  ent_res    :: VHDLSignalMapElement         -- A mapping of the function result to port names
+  ent_args   :: [Port],      -- A mapping of each function argument to port names
+  ent_res    :: Port         -- A mapping of the function result to port names
 } deriving (Show);
 
 -- A orderable equivalent of CoreSyn's Type for use as a map key
@@ -42,11 +38,14 @@ instance Eq OrdType where
 instance Ord OrdType where
   compare (OrdType a) (OrdType b) = Type.tcCmpType a b
 
--- A map of a Core type to the corresponding type name
-type TypeMap = Map.Map OrdType (AST.VHDLId, Either AST.TypeDef AST.SubtypeIn)
+data HType = StdType OrdType |
+             ADTType String [HType] |
+             VecType Int HType |
+             BuiltinType String
+  deriving (Eq, Ord)
 
--- A map of Elem types to the corresponding VHDL Id for the Vector
-type ElemTypeMap = Map.Map OrdType (AST.VHDLId, AST.TypeDef)
+-- A map of a Core type to the corresponding type name
+type TypeMap = Map.Map HType (AST.VHDLId, Either AST.TypeDef AST.SubtypeIn)
 
 -- A map of a vector Core element type and function name to the coressponding
 -- VHDLId of the function and the function body.
@@ -55,13 +54,24 @@ type TypeFunMap = Map.Map (OrdType, String) (AST.VHDLId, AST.SubProgBody)
 -- A map of a Haskell function to a hardware signature
 type SignatureMap = Map.Map CoreSyn.CoreBndr Entity
 
-data VHDLState = VHDLState {
+data TypeState = TypeState {
   -- | A map of Core type -> VHDL Type
   vsTypes_      :: TypeMap,
-  -- | A map of Elem types -> VHDL Vector Id
-  vsElemTypes_   :: ElemTypeMap,
+  -- | A list of type declarations
+  vsTypeDecls_  :: [AST.PackageDecItem],
   -- | A map of vector Core type -> VHDL type function
-  vsTypeFuns_   :: TypeFunMap,
+  vsTypeFuns_   :: TypeFunMap
+}
+-- Derive accessors
+$( Data.Accessor.Template.deriveAccessors ''TypeState )
+-- Define an empty TypeState
+emptyTypeState = TypeState Map.empty [] Map.empty
+-- Define a session
+type TypeSession = State.State TypeState
+
+data VHDLState = VHDLState {
+  -- | A subtype with typing info
+  vsType_       :: TypeState,
   -- | A map of HsFunction -> hardware signature (entity name, port names,
   --   etc.)
   vsSignatures_ :: SignatureMap
@@ -73,15 +83,12 @@ $( Data.Accessor.Template.deriveAccessors ''VHDLState )
 -- | The state containing a VHDL Session
 type VHDLSession = State.State VHDLState
 
--- | A substate containing just the types
-type TypeState = State.State TypeMap
-
 -- A function that generates VHDL for a builtin function
 type BuiltinBuilder = 
-  CoreSyn.CoreBndr -- ^ The destination value
+  (Either CoreSyn.CoreBndr AST.VHDLName) -- ^ The destination signal and it's original type
   -> CoreSyn.CoreBndr -- ^ The function called
-  -> [CoreSyn.CoreExpr] -- ^ The value arguments passed (excluding type and
-                        --   dictionary arguments).
+  -> [Either CoreSyn.CoreExpr AST.Expr] -- ^ The value arguments passed (excluding type and
+                    --   dictionary arguments).
   -> VHDLSession [AST.ConcSm] -- ^ The resulting concurrent statements.
 
 -- A map of a builtin function to VHDL function builder