import qualified ForSyDe.Backend.VHDL.AST as AST
-- Local imports
-import FlattenTypes
-import HsValueMap
-type VHDLSignalMapElement = (Maybe (AST.VHDLId, AST.TypeMark))
--- | A mapping from a haskell structure to the corresponding VHDL port
--- signature, or Nothing for values that do not translate to a port.
-type VHDLSignalMap = HsValueMap VHDLSignalMapElement
+-- A description of a port of an entity
+type Port = (AST.VHDLId, AST.TypeMark)
-- A description of a VHDL entity. Contains both the entity itself as well as
-- info on how to map a haskell value (argument / result) on to the entity's
-- ports.
data Entity = Entity {
ent_id :: AST.VHDLId, -- The id of the entity
- ent_args :: [VHDLSignalMapElement], -- A mapping of each function argument to port names
- ent_res :: VHDLSignalMapElement -- A mapping of the function result to port names
+ ent_args :: [Port], -- A mapping of each function argument to port names
+ ent_res :: Port -- A mapping of the function result to port names
} deriving (Show);
-- A orderable equivalent of CoreSyn's Type for use as a map key
-- | A substate containing just the types
type TypeState = State.State TypeMap
-type Builder = Either (CoreSyn.CoreBndr -> [AST.Expr] -> VHDLSession AST.Expr) (Entity -> [CoreSyn.CoreBndr] -> VHDLSession AST.GenerateSm)
+-- A function that generates VHDL for a builtin function
+type BuiltinBuilder =
+ (Either CoreSyn.CoreBndr AST.VHDLName) -- ^ The destination signal and it's original type
+ -> CoreSyn.CoreBndr -- ^ The function called
+ -> [Either CoreSyn.CoreExpr AST.Expr] -- ^ The value arguments passed (excluding type and
+ -- dictionary arguments).
+ -> VHDLSession [AST.ConcSm] -- ^ The resulting concurrent statements.
-- A map of a builtin function to VHDL function builder
-type NameTable = Map.Map String (Int, Builder )
+type NameTable = Map.Map String (Int, BuiltinBuilder )
-- vim: set ts=8 sw=2 sts=2 expandtab: