Merge branch 'cλash' of http://git.stderr.nl/matthijs/projects/master-project

[matthijs/master-project/cλash.git] / VHDLTypes.hs

diff --git a/VHDLTypes.hs b/VHDLTypes.hs
index 54baf47ef4ba31ec20e3f73378afbfec19a779ea..e517a8ba08166d6c5800bdb5d4f41b3e4ab74876 100644 (file)
--- a/VHDLTypes.hs
+++ b/VHDLTypes.hs
@@ -12,6 +12,7 @@ import qualified Data.Accessor.Template
 
 -- GHC API imports
 import qualified Type
+import qualified CoreSyn
 
 -- ForSyDe imports
 import qualified ForSyDe.Backend.VHDL.AST as AST
@@ -20,17 +21,18 @@ import qualified ForSyDe.Backend.VHDL.AST as AST
 import FlattenTypes
 import HsValueMap
 
+type VHDLSignalMapElement = (Maybe (AST.VHDLId, AST.TypeMark))
 -- | A mapping from a haskell structure to the corresponding VHDL port
 --   signature, or Nothing for values that do not translate to a port.
-type VHDLSignalMap = HsValueMap (Maybe (AST.VHDLId, AST.TypeMark))
+type VHDLSignalMap = HsValueMap VHDLSignalMapElement
 
 -- A description of a VHDL entity. Contains both the entity itself as well as
 -- info on how to map a haskell value (argument / result) on to the entity's
 -- ports.
-data Entity = Entity {
+data Entity = Entity { 
   ent_id     :: AST.VHDLId,           -- The id of the entity
-  ent_args   :: [VHDLSignalMap],      -- A mapping of each function argument to port names
-  ent_res    :: VHDLSignalMap         -- A mapping of the function result to port names
+  ent_args   :: [VHDLSignalMapElement],      -- A mapping of each function argument to port names
+  ent_res    :: VHDLSignalMapElement         -- A mapping of the function result to port names
 } deriving (Show);
 
 -- A orderable equivalent of CoreSyn's Type for use as a map key
@@ -40,24 +42,37 @@ instance Eq OrdType where
 instance Ord OrdType where
   compare (OrdType a) (OrdType b) = Type.tcCmpType a b
 
--- A map of a Core type to the corresponding type name (and optionally, it's
--- declaration for non-primitive types).
+-- A map of a Core type to the corresponding type name
 type TypeMap = Map.Map OrdType (AST.VHDLId, AST.TypeDec)
 
+-- A map of a vector Core type to the coressponding VHDL functions
+type TypeFunMap = Map.Map OrdType [AST.SubProgBody]
+
 -- A map of a Haskell function to a hardware signature
-type SignatureMap = Map.Map HsFunction Entity
+type SignatureMap = Map.Map String Entity
+
+-- A map of a builtin function to VHDL function builder 
+type NameTable = Map.Map String (Int, [AST.Expr] -> AST.Expr )
 
 data VHDLSession = VHDLSession {
   -- | A map of Core type -> VHDL Type
-  vsTypes_ :: TypeMap,
+  vsTypes_      :: TypeMap,
+  -- | A map of vector Core type -> VHDL type function
+  vsTypeFuns_   :: TypeFunMap,
   -- | A map of HsFunction -> hardware signature (entity name, port names,
   --   etc.)
-  vsSignatures_ :: SignatureMap
+  vsSignatures_ :: SignatureMap,
+  -- | A map of Vector HsFunctions -> VHDL function call
+  vsNameTable_  :: NameTable
 }
 
 -- Derive accessors
 $( Data.Accessor.Template.deriveAccessors ''VHDLSession )
 
+-- | The state containing a VHDL Session
 type VHDLState = State.State VHDLSession
 
+-- | A substate containing just the types
+type TypeState = State.State TypeMap
+
 -- vim: set ts=8 sw=2 sts=2 expandtab: