-- A map of Elem types to the corresponding VHDL Id for the Vector
type ElemTypeMap = Map.Map OrdType (AST.VHDLId, AST.TypeDef)
--- A map of a vector Core type to the coressponding VHDL functions
-type TypeFunMap = Map.Map OrdType [AST.SubProgBody]
+-- A map of a vector Core element type and function name to the coressponding
+-- VHDLId of the function and the function body.
+type TypeFunMap = Map.Map (OrdType, String) (AST.VHDLId, AST.SubProgBody)
-- A map of a Haskell function to a hardware signature
-type SignatureMap = Map.Map String Entity
+type SignatureMap = Map.Map CoreSyn.CoreBndr Entity
--- A map of a builtin function to VHDL function builder
-type NameTable = Map.Map String (Int, [AST.Expr] -> AST.Expr )
-
-data VHDLSession = VHDLSession {
+data VHDLState = VHDLState {
-- | A map of Core type -> VHDL Type
vsTypes_ :: TypeMap,
-- | A map of Elem types -> VHDL Vector Id
vsTypeFuns_ :: TypeFunMap,
-- | A map of HsFunction -> hardware signature (entity name, port names,
-- etc.)
- vsSignatures_ :: SignatureMap,
- -- | A map of Vector HsFunctions -> VHDL function call
- vsNameTable_ :: NameTable
+ vsSignatures_ :: SignatureMap
}
-- Derive accessors
-$( Data.Accessor.Template.deriveAccessors ''VHDLSession )
+$( Data.Accessor.Template.deriveAccessors ''VHDLState )
-- | The state containing a VHDL Session
-type VHDLState = State.State VHDLSession
+type VHDLSession = State.State VHDLState
-- | A substate containing just the types
type TypeState = State.State TypeMap
+type Builder = Either (CoreSyn.CoreBndr -> [AST.Expr] -> VHDLSession AST.Expr) (Entity -> [CoreSyn.CoreBndr] -> VHDLSession AST.GenerateSm)
+
+-- A map of a builtin function to VHDL function builder
+type NameTable = Map.Map String (Int, Builder )
+
-- vim: set ts=8 sw=2 sts=2 expandtab: