import qualified ForSyDe.Backend.VHDL.AST as AST
-- Local imports
-import FlattenTypes
-import HsValueMap
-type VHDLSignalMapElement = (Maybe (AST.VHDLId, AST.TypeMark))
--- | A mapping from a haskell structure to the corresponding VHDL port
--- signature, or Nothing for values that do not translate to a port.
-type VHDLSignalMap = HsValueMap VHDLSignalMapElement
+-- A description of a port of an entity
+type Port = (AST.VHDLId, AST.TypeMark)
-- A description of a VHDL entity. Contains both the entity itself as well as
-- info on how to map a haskell value (argument / result) on to the entity's
-- ports.
data Entity = Entity {
ent_id :: AST.VHDLId, -- The id of the entity
- ent_args :: [VHDLSignalMapElement], -- A mapping of each function argument to port names
- ent_res :: VHDLSignalMapElement -- A mapping of the function result to port names
+ ent_args :: [Port], -- A mapping of each function argument to port names
+ ent_res :: Port -- A mapping of the function result to port names
} deriving (Show);
-- A orderable equivalent of CoreSyn's Type for use as a map key
-- A map of a Core type to the corresponding type name
type TypeMap = Map.Map OrdType (AST.VHDLId, Either AST.TypeDef AST.SubtypeIn)
--- A map of Elem types to the corresponding VHDL Id for the Vector
-type ElemTypeMap = Map.Map OrdType (AST.VHDLId, AST.TypeDef)
-
-- A map of a vector Core element type and function name to the coressponding
-- VHDLId of the function and the function body.
type TypeFunMap = Map.Map (OrdType, String) (AST.VHDLId, AST.SubProgBody)
data VHDLState = VHDLState {
-- | A map of Core type -> VHDL Type
vsTypes_ :: TypeMap,
- -- | A map of Elem types -> VHDL Vector Id
- vsElemTypes_ :: ElemTypeMap,
-- | A map of vector Core type -> VHDL type function
vsTypeFuns_ :: TypeFunMap,
-- | A map of HsFunction -> hardware signature (entity name, port names,
-- A function that generates VHDL for a builtin function
type BuiltinBuilder =
- CoreSyn.CoreBndr -- ^ The destination value
+ (Either CoreSyn.CoreBndr AST.VHDLName) -- ^ The destination signal and it's original type
-> CoreSyn.CoreBndr -- ^ The function called
- -> [CoreSyn.CoreExpr] -- ^ The value arguments passed (excluding type and
- -- dictionary arguments).
+ -> [Either CoreSyn.CoreExpr AST.Expr] -- ^ The value arguments passed (excluding type and
+ -- dictionary arguments).
-> VHDLSession [AST.ConcSm] -- ^ The resulting concurrent statements.
-- A map of a builtin function to VHDL function builder