Partly fixed implementation for integer literals.

[matthijs/master-project/cλash.git] / VHDLTypes.hs

diff --git a/VHDLTypes.hs b/VHDLTypes.hs
index 4a1b01719300f0cc9dab8de620a19ed18b2dc21f..b9db66a485220276f060c18edcb9c1419efa1fa3 100644 (file)
--- a/VHDLTypes.hs
+++ b/VHDLTypes.hs
@@ -41,6 +41,9 @@ instance Ord OrdType where
 data HType = StdType OrdType |
              ADTType String [HType] |
              VecType Int HType |
+             SizedWType Int |
+             RangedWType Int |
+             SizedIType Int |
              BuiltinType String
   deriving (Eq, Ord)
 
@@ -54,13 +57,27 @@ type TypeFunMap = Map.Map (OrdType, String) (AST.VHDLId, AST.SubProgBody)
 -- A map of a Haskell function to a hardware signature
 type SignatureMap = Map.Map CoreSyn.CoreBndr Entity
 
-data VHDLState = VHDLState {
+type TfpIntMap = Map.Map OrdType Int
+
+data TypeState = TypeState {
   -- | A map of Core type -> VHDL Type
   vsTypes_      :: TypeMap,
   -- | A list of type declarations
   vsTypeDecls_  :: [AST.PackageDecItem],
   -- | A map of vector Core type -> VHDL type function
   vsTypeFuns_   :: TypeFunMap,
+  vsTfpInts_    :: TfpIntMap
+}
+-- Derive accessors
+$( Data.Accessor.Template.deriveAccessors ''TypeState )
+-- Define an empty TypeState
+emptyTypeState = TypeState Map.empty [] Map.empty Map.empty
+-- Define a session
+type TypeSession = State.State TypeState
+
+data VHDLState = VHDLState {
+  -- | A subtype with typing info
+  vsType_       :: TypeState,
   -- | A map of HsFunction -> hardware signature (entity name, port names,
   --   etc.)
   vsSignatures_ :: SignatureMap
@@ -72,9 +89,6 @@ $( Data.Accessor.Template.deriveAccessors ''VHDLState )
 -- | The state containing a VHDL Session
 type VHDLSession = State.State VHDLState
 
--- | A substate containing just the types
-type TypeState = State.State TypeMap
-
 -- A function that generates VHDL for a builtin function
 type BuiltinBuilder = 
   (Either CoreSyn.CoreBndr AST.VHDLName) -- ^ The destination signal and it's original type