Great speed-up in type generation

[matthijs/master-project/cλash.git] / VHDLTypes.hs

diff --git a/VHDLTypes.hs b/VHDLTypes.hs
index 0bc1a5e339ef9cf32aa92554e1c30d12db972ff3..b4c1d6981c2f757df4fb7c5049375aa4845bcb59 100644 (file)
--- a/VHDLTypes.hs
+++ b/VHDLTypes.hs
@@ -13,6 +13,7 @@ import qualified Data.Accessor.Template
 -- GHC API imports
 import qualified Type
 import qualified CoreSyn
+import qualified HscTypes
 
 -- ForSyDe imports
 import qualified ForSyDe.Backend.VHDL.AST as AST
@@ -40,7 +41,10 @@ instance Ord OrdType where
 
 data HType = StdType OrdType |
              ADTType String [HType] |
-             VecType Int HType |
+             VecType OrdType HType |
+             SizedWType Int |
+             RangedWType Int |
+             SizedIType Int |
              BuiltinType String
   deriving (Eq, Ord)
 
@@ -63,12 +67,11 @@ data TypeState = TypeState {
   vsTypeDecls_  :: [AST.PackageDecItem],
   -- | A map of vector Core type -> VHDL type function
   vsTypeFuns_   :: TypeFunMap,
-  vsTfpInts_    :: TfpIntMap
+  vsTfpInts_    :: TfpIntMap,
+  vsHscEnv_     :: HscTypes.HscEnv
 }
 -- Derive accessors
 $( Data.Accessor.Template.deriveAccessors ''TypeState )
--- Define an empty TypeState
-emptyTypeState = TypeState Map.empty [] Map.empty Map.empty
 -- Define a session
 type TypeSession = State.State TypeState