-- GHC API imports
import qualified Type
import qualified CoreSyn
+import qualified HscTypes
-- ForSyDe imports
import qualified ForSyDe.Backend.VHDL.AST as AST
data HType = StdType OrdType |
ADTType String [HType] |
- VecType Int HType |
+ VecType OrdType HType |
+ SizedWType Int |
+ RangedWType Int |
+ SizedIType Int |
BuiltinType String
deriving (Eq, Ord)
-- A map of a Haskell function to a hardware signature
type SignatureMap = Map.Map CoreSyn.CoreBndr Entity
+type TfpIntMap = Map.Map OrdType Int
+
data TypeState = TypeState {
-- | A map of Core type -> VHDL Type
vsTypes_ :: TypeMap,
-- | A list of type declarations
vsTypeDecls_ :: [AST.PackageDecItem],
-- | A map of vector Core type -> VHDL type function
- vsTypeFuns_ :: TypeFunMap
+ vsTypeFuns_ :: TypeFunMap,
+ vsTfpInts_ :: TfpIntMap,
+ vsHscEnv_ :: HscTypes.HscEnv
}
-- Derive accessors
$( Data.Accessor.Template.deriveAccessors ''TypeState )
--- Define an empty TypeState
-emptyTypeState = TypeState Map.empty [] Map.empty
-- Define a session
type TypeSession = State.State TypeState