-- GHC API imports
import qualified Type
+import qualified CoreSyn
-- ForSyDe imports
import qualified ForSyDe.Backend.VHDL.AST as AST
-- ports.
data Entity = Entity {
ent_id :: AST.VHDLId, -- The id of the entity
- ent_args :: [VHDLSignalMap], -- A mapping of each function argument to port names
- ent_res :: VHDLSignalMap -- A mapping of the function result to port names
+ ent_args :: [VHDLSignalMapElement], -- A mapping of each function argument to port names
+ ent_res :: VHDLSignalMapElement -- A mapping of the function result to port names
} deriving (Show);
-- A orderable equivalent of CoreSyn's Type for use as a map key
type TypeMap = Map.Map OrdType (AST.VHDLId, AST.TypeDec)
-- A map of a Haskell function to a hardware signature
-type SignatureMap = Map.Map HsFunction Entity
+type SignatureMap = Map.Map String Entity
data VHDLSession = VHDLSession {
-- | A map of Core type -> VHDL Type