Remove createArchitecture from the VHDLState Monad.

[matthijs/master-project/cλash.git] / VHDLTypes.hs

diff --git a/VHDLTypes.hs b/VHDLTypes.hs
index 26ed823d904f35dd6653513f84cf2788e81ddac2..74084864dc8c3c9f8d8a1aa27a433e4a7cf8132a 100644 (file)
--- a/VHDLTypes.hs
+++ b/VHDLTypes.hs
@@ -19,5 +19,6 @@ data Entity = Entity {
   ent_id     :: AST.VHDLId,           -- The id of the entity
   ent_args   :: [VHDLSignalMap],      -- A mapping of each function argument to port names
   ent_res    :: VHDLSignalMap,        -- A mapping of the function result to port names
-  ent_decl   :: Maybe AST.EntityDec   -- The actual entity declaration. Can be empty for builtin functions.
-}
+  ent_decl   :: Maybe AST.EntityDec,  -- The actual entity declaration. Can be empty for builtin functions.
+  ent_pkg_decl :: Maybe AST.PackageDec -- A package declaration with types for this entity
+} deriving (Show);